View ADC12DJ3200ZEG_9061490.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. adc12dj3200 slvsd97 ? june 2017 adc12dj3200 6.4-gsps single channel or 3.2-gsps dual channel, 12-bit, rf-sampling analog-to-digital converter (adc) 1 1 features 1 ? adc core: ? 12-bit resolution ? up to 6.4 gsps in single channel mode ? up to 3.2 gsps in dual channel mode ? buffered analog inputs with v cmi of 0 v ? analog input bandwidth (-3 db): 8.0 ghz ? usable input frequency range: > 10 ghz ? full-scale input voltage (v fs , default): 0.8 v pp ? noise floor (no signal, v fs = 1.0 v pp ): ? dual channel mode: -151.8 dbfs/hz ? single channel mode: -154.6 dbfs/hz ? noiseless aperture delay (t ad ) adjustment ? precise sampling control: 19-fs step ? temperature and voltage invariant delays ? easy-to-use synchronization features ? automatic sysref timing calibration ? timestamp for sample marking ? jesd204b serial data interface ? supports subclass 0 and 1 ? maximum lane rate: 12.8 gbps ? up to 16 lanes allows reduced lane rate ? digital down-converters in dual channel mode ? real output: ddc bypass or 2x decimation ? complex output: 4x, 8x or 16x decimation ? four independent 32-bit ncos per ddc ? power consumption: 3.0 w ? power supplies: 1.1 v, 1.9 v 2 applications ? communications testers (802.11ad, 5g) ? satellite communications (satcom) ? phased array radar, sigint and elint ? synthetic aperture radar (sar) ? time-of-flight and lidar distance measurement ? oscilloscopes and wideband digitizers ? rf sampling software defined radio (sdr) 3 description adc12dj3200 is an rf-sampling giga-sample adc that can directly sample input frequencies from dc to above 10 ghz. in dual channel mode, adc12dj3200 can sample up to 3200-msps and in single channel mode up to 6400-msps. programmable tradeoffs in channel count (dual channel mode) and nyquist bandwidth (single channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. full power input bandwidth (- 3 db) of 8.0 ghz, with usable frequencies exceeding the -3 db point in both dual and single channel modes, allows direct rf sampling of l-band, s-band, c-band and x-band for frequency agile systems. adc12dj3200 uses a high speed jesd204b output interface with up to 16 serialized lanes and subclass- 1 compliance for deterministic latency and multi- device synchronization. the serial output lanes support up to 12.8 gbps and can be configured to trade-off bit rate and number of lanes. innovative synchronization features, including noiseless aperture delay (t ad ) adjustment and sysref windowing, simplify system design for phased array radar and mimo communications. optional digital down converters (ddcs) in dual channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only). device information (1) part number package body size (nom) adc12dj3200 fcbga (144) 10.00 mm x 10.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. adc12dj3200 measured input bandwidth productfolder input frequency (ghz) normalized gain response (db) 0 2 4 6 8 10 12 -15 -12 -9 -6 -3 0 3 d_bw single channel mode dual channel mode support &community tools & software technical documents ordernow
2 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 9 6.1 absolute maximum ratings ...................................... 9 6.2 esd ratings .............................................................. 9 6.3 recommended operating conditions ..................... 10 6.4 thermal information ................................................ 11 6.5 electrical characteristics - dc specifications ......... 12 6.6 electrical characteristics - power consumption ..... 14 6.7 electrical characteristics - ac specifications ......... 15 6.8 timing requirements .............................................. 22 6.9 switching characteristics ........................................ 23 6.10 typical characteristics .......................................... 27 7 detailed description ............................................ 38 7.1 overview ................................................................. 38 7.2 functional block diagrams ..................................... 39 7.3 feature description ................................................. 39 7.4 device functional modes ........................................ 61 7.5 programming ........................................................... 79 7.6 register maps ......................................................... 80 8 application and implementation ...................... 137 8.1 application information .......................................... 137 8.2 typical application ............................................... 137 8.3 initialization set up .............................................. 140 9 power supply recommendations .................... 140 10 layout ................................................................. 142 10.1 layout guidelines ............................................... 142 10.2 layout example .................................................. 143 11 device and documentation support ............... 146 11.1 device support .................................................. 146 11.2 related links ...................................................... 146 11.3 receiving notification of documentation updates .................................................................. 146 11.4 community resources ........................................ 146 11.5 trademarks ......................................................... 146 11.6 electrostatic discharge caution .......................... 146 11.7 glossary .............................................................. 146 12 mechanical, packaging, and orderable information ......................................................... 147 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes may 2017 * advance information release june 2017 * production data release
3 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions aav package 144-ball flip chip bga top view agnd tmstp+ ina+ tmstp- syncse bg va19 va19 ina- da3+ va11 ncoa0 ora0 ncoa1 ora1 da3- da2+ da2- da5+ da1+ da5- da1- va19 clk+ va19 va19 va19 clk- va19 va19 va19 va19 caltrig scs calstat sclk sdi sdo da4+ da0+ da4- da0- db4- db0- db4+ db0+ sysref+ tdiode+ va19 tdiode- va19 sysref- inb+ pd ncob1 orb1 ncob0 orb0 inb- db7+ db3+ db5- db1- db5+ db1+ db7- db6+ db3- db2+ db6- db2- a b c d e f g h j k l m 12 11 10 9 8 7 6 5 4 3 2 1 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd va11 va11 va11 va11 va11 va11 va11 va11 va11 va11 va11 vd11 vd11 vd11 vd11 vd11 vd11 vd11 vd11 da7+ da7- da6+ da6- agnd vd11 vd11
4 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions pin i/o description name no. agnd a1, a2, a3, a6, a7, b2, b3, b4, b5, b6, b7, c6, d1, d6, e1, e6, f2, f3, f6, g2, g3, g6, h1, h6, j1, j6, l2, l3, l4, l5, l6, l7, m1, m2, m3, m6, m7 ? analog supply ground. agnd and dgnd should be tied to a common ground plane (gnd) on circuit board. dgnd a12, b12, d9, d10, f9, f10, g9, g10, j9, j10, l12, m12 ? digital supply ground. agnd and dgnd should be tied to a common ground plane (gnd) on circuit board. bg c3 o bandgap voltage output. this pin is capable of sourcing only small currents and driving limited capacitive loads as specified in recommended operating conditions . this pin can be left disconnected if not used. calstat f7 o foreground calibration status output or device alarm output. functionality is programmed through cal_status_sel. this pin can be left disconnected if not used. caltrig e7 i foreground calibration trigger input. this pin is only used if hardware calibration triggering is selected in cal_trig_en, otherwise software triggering is performed using cal_soft_trig. this pin should be tied to gnd if not used. clk+ f1 i device (sampling) clock positive input. the clock signal is strongly recommended to be ac coupled to this input for best performance. in single channel mode, the analog input signal is sampled on both rising and falling edges. in dual channel mode, the analog signal is sampled on the rising edge. this differential input has an internal untrimmed 100- differential termination and is self-biased to the optimal input common mode voltage as long as devclk_lvpecl_en is set to 0. clk- g1 i device (sampling) clock negative input. strongly recommended to use ac coupling for best performance. da0+ e12 o high-speed serialized-data output for channel a, lane 0, positive connection. this differential output must be ac-coupled and should always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da0- f12 o high-speed serialized-data output for channel a, lane 0, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da1+ c12 o high-speed serialized-data output for channel a, lane 1, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da1- d12 o high-speed serialized-data output for channel a, lane 1, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da2+ a10 o high-speed serialized-data output for channel a, lane 2, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da2- a11 o high-speed serialized-data output for channel a, lane 2, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da3+ a8 o high-speed serialized-data output for channel a, lane 3, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation.
5 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. da3- a9 o high-speed serialized-data output for channel a, lane 3, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da4+ e11 o high-speed serialized-data output for channel a, lane 4, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da4- f11 o high-speed serialized-data output for channel a, lane 4, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da5+ c11 o high-speed serialized-data output for channel a, lane 5, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da5- d11 o high-speed serialized-data output for channel a, lane 5, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da6+ b10 o high-speed serialized-data output for channel a, lane 6, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da6- b11 o high-speed serialized-data output for channel a, lane 6, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da7+ b8 o high-speed serialized-data output for channel a, lane 7, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. da7- b9 o high-speed serialized-data output for channel a, lane 7, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db0+ h12 o high-speed serialized-data output for channel b, lane 0, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db0- g12 o high-speed serialized-data output for channel b, lane 0, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db1+ k12 o high-speed serialized-data output for channel b, lane 1, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db1- j12 o high-speed serialized-data output for channel b, lane 1, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db2+ m10 o high-speed serialized-data output for channel b, lane 2, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db2- m11 o high-speed serialized-data output for channel b, lane 2, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db3+ m8 o high-speed serialized-data output for channel b, lane 3, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db3- m9 o high-speed serialized-data output for channel b, lane 3, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation.
6 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. db4+ h11 o high-speed serialized-data output for channel b, lane 4, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db4- g11 o high-speed serialized-data output for channel b, lane 4, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db5+ k11 o high-speed serialized-data output for channel b, lane 5, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db5- j11 o high-speed serialized-data output for channel b, lane 5, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db6+ l10 o high-speed serialized-data output for channel b, lane 6, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db6- l11 o high-speed serialized-data output for channel b, lane 6, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db7+ l8 o high-speed serialized-data output for channel b, lane 7, positive connection. this differential output must be ac-coupled and must always be terminated with a 100- differential termination at the receiver. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. db7- l9 o high-speed serialized-data output for channel b, lane 7, negative connection. this pin can be left disconnected if not used. see note beneath recommended operating conditions for information regarding reliable serializer operation. ina+ a4 i channel a analog input positive connection. the differential full-scale input voltage is determined by the fs_range_a register (see full-scale voltage (v fs ) adjustment ). this input is terminated to ground through a 50- termination resistor. the input common mode voltage should typically be set to 0 v (gnd) and should follow the recommendations in recommended operating conditions . this pin can be left disconnected if not used. note use of ina+/ ? is recommended in single channel mode for optimized performance. ina- a5 i channel a analog input negative connection. see ina+ for detailed description. this input is terminated to ground through a 50- termination resistor. this pin can be left disconnected if not used. inb+ m4 i channel b analog input positive connection. the differential full-scale input voltage is determined by the fs_range_b register (see full-scale voltage (v fs ) adjustment ). this input is terminated to ground through a 50- termination resistor. the input common mode voltage should typically be set to 0 v (gnd) and should follow the recommendations in recommended operating conditions . this pin can be left disconnected if not used. use of ina+/- is recommended for single channel mode for optimized performance. inb- m5 i channel b analog input negative connection. see inb+ for detailed description. this input is terminated to ground through a 50- termination resistor. this pin can be left disconnected if not used. ncoa0 c7 i lsb of nco selection control for ddc a. ncoa0 and ncoa1 select which nco, of a possible four ncos, is used for digital mixing when using a complex output jmode. the remaining unselected ncos continue to run to maintain phase coherency and can be swapped in by changing the values of ncoa0 and ncoa1 (when cmode = 1). this is an asynchronous input. see nco fast frequency hopping (ffh) and nco selection for more information. this pin should be tied to gnd if not used. ncoa1 d7 i msb of nco selection control for ddc a. this pin should be tied to gnd if not used.
7 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. ncob0 k7 i lsb of nco selection control for ddc b. ncob0 and ncob1 select which nco, of a possible four ncos, is used for digital mixing when using a complex output jmode. the remaining unselected ncos continue to run to maintain phase coherency and can be swapped in by changing the values of ncob0 and ncob1 (when cmode = 1). this is an asynchronous input. see nco fast frequency hopping (ffh) and nco selection for more information. this pin should be tied to gnd if not used. ncob1 j7 i msb of nco selection control for ddc b. this pin should be tied to gnd if not used. ora0 c8 o fast over-range detection status for channel a for ovr_t0 threshold. when the analog input exceeds the threshold programmed into ovr_t0, this status indicator will go high. the minimum pulse duration is set by ovr_n. see adc over-range detection for more information. this pin can be left disconnected if not used. ora1 d8 o fast over-range detection status for channel a for ovr_t1 threshold. when the analog input exceeds the threshold programmed into ovr_t1, this status indicator will go high. the minimum pulse duration is set by ovr_n. see adc over-range detection for more information. this pin can be left disconnected if not used. orb0 k8 o fast over-range detection status for channel b for ovr_t0 threshold. when the analog input exceeds the threshold programmed into ovr_t0, this status indicator will go high. the minimum pulse duration is set by ovr_n. see adc over-range detection for more information. this pin can be left disconnected if not used. orb1 j8 o fast over-range detection status for channel b for ovr_t1 threshold. when the analog input exceeds the threshold programmed into ovr_t1, this status indicator will go high. the minimum pulse duration is set by ovr_n. see adc over-range detection for more information. this pin can be left disconnected if not used. pd k6 i this pin disables all analog circuits and serializer outputs when set high for temperature diode calibration only. this pin should not be used to power down the device for power savings. this pin should be tied to gnd during normal operation. see note beneath recommended operating conditions for more information. sclk f8 i serial interface clock. this pin functions as the serial-interface clock input which clocks the serial programming data in and out. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. scs e8 i serial interface chip select active low input. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. this pin has a 82-k pull-up resistor to vd11. sdi g8 i serial interface data input. using the serial interface describes the serial interface in more detail. supports 1.1 v and 1.8 v cmos levels. sdo h8 o serial interface data output. using the serial interface describes the serial interface in more detail. this pin is high impedance during normal device operation. this pin outputs 1.9-v cmos levels during serial interface read operations. this pin can be left disconnected if not used. syncse c2 i single-ended jesd204b sync signal. this input is an active low input that is used to initialize the jesd204b serial link when sync_sel is set to 0. when toggled low it initiates code group synchronization ( code group synchronization (cgs) ). after code group synchronization, it must be toggled high to start the initial lane alignment sequence ( initial lane alignment sequence (ilas) ). a differential sync signal can be used instead by setting sync_sel to 1 and using tmstp+/ ? as a differential sync input. this pin should be tied to gnd if differential sync (tmstp+/-) is used as the jesd204b sync signal. sysref+ k1 i sysref positive input used to achieve synchronization and deterministic latency across the jesd204b interface. this differential input (sysref+ to sysref ? ) has an internal untrimmed 100- differential termination and can be ac coupled when sysref_lvpecl_en is set to 0. this input is self-biased when sysref_lvpecl_en is set to 0. the termination changes to 50 to ground on each input pin (sysref+ and sysref ? ) and can be dc coupled when sysref_lvpecl_en is set to 1. this input is not self-biased when sysref_lvpecl_en is set to 1 and must be biased externally to the input common mode voltage range provided in recommended operating conditions . sysref- l1 i sysref negative input. tdiode+ k2 i temperature diode positive (anode) connection. an external temperature sensor can be connected to tdiode+ and tdiode- to monitor the junction temperature of the device. this pin can be left disconnected if not used. tdiode- k3 i temperature diode negative (cathode) connection. this pin can be left disconnected if not used.
8 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. tmstp+ b1 i timestamp input positive connection or differential jesd204b sync positive connection. this input is a timestamp input, used to mark a specific sample, when timestamp_en is set to 1. this differential input is used as the jesd204b sync signal input when sync_sel is set 1. it can be used as both timestamp and differential sync input at the same time, allowing feedback of the sync signal using the timestamp mechanism. tmstp+/ ? uses active low signaling when used as jesd204b sync. for additional usage information refer to timestamp . tmstp_recv_en must be set to 1 to use this input. this differential input (tmstp+ to tmstp ? ) has an internal untrimmed 100- differential termination and can be ac coupled when tmstp_lvpecl_en is set to 0. the termination changes to 50 to ground on each input pin (tmstp+ and tmstp ? ) and can be dc coupled when tmstp_lvpecl_en is set to 1. this pin is not self-biased and therefore it must be externally biased for both ac and dc coupled configurations. the common mode voltage must be within the range provided in recommended operating conditions when both ac and dc coupled. this pin can be left disconnected and disabled (tmstp_recv_en = 0) if syncse is used for jesd204b sync and timestamp is not required. tmstp- c1 i timestamp input positive connection or differential jesd204b sync negative connection. this pin can be left disconnected and disabled (tmstp_recv_en = 0) if syncse is used for jesd204b sync and timestamp is not required. va11 c5, d2, d3, d5, e5, f5, g5, h5, j2, j3, j5, k5 i 1.1-v analog supply. va19 c4, d4, e2, e3, e4, f4, g4, h2, h3, h4, j4, k4 i 1.9-v analog supply. vd11 c9, c10, e9, e10, g7, h7, h9, h10, k9, k10 i 1.1-v digital supply.
9 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) measured to agnd. (3) measured to dgnd. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range va19 (2) -0.3 2.35 v va11 (2) -0.3 1.32 v vd11 (3) -0.3 1.32 v voltage between vd11 and va11 -1.32 1.32 v voltage between agnd and dgnd -0.1 0.1 v terminal voltage range da0...7+, da0...7-, db0...7+, db0...7-, tmstp+, tmstp ? (3) -0.5 min(1.32, vd11+0.5) v clk+, clk ? , sysref+, sysref ? (2) -0.5 min(1.32, va11+0.5) v bg, tdiode+, tdiode ? (2) -0.5 min(2.35, va19+0.5) v ina+, ina ? , inb+, inb ? (2) -1 1 v calstat, caltrig, ncoa0, ncoa1, ncob0, ncob1, ora0, ora1, orb0, orb1, pd, sclk, scs, sdi, sdo, syncse (2) -0.5 va19+0.5 v peak input current (any input except ina+, ina ? , inb+, inb ? ) -25 25 ma peak input current (ina+, ina ? , inb+, inb ? ) -50 50 ma peak rf input power (ina+, ina ? , inb+, inb ? ) single-ended with z s-se = 50 or differential with z s-diff = 100 16.4 dbm peak total input current (sum of absolute value of all currents forced in or out, not including power supply current) 100 ma operating junction temperature, t j 150 c storage temperature, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2500 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1000
10 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) measured to agnd. (2) measured to dgnd. (3) it is strongly recommended that clk+/ ? be ac coupled with devclk_lvpecl_en set to 0 to allow clk+/ ? to self bias to the optimal input common mode voltage for best performnace. ti recommends ac coupling for sysref+/ ? unless dc coupling is required, in which case lvpecl input mode must be used (sysref_lvpecl_en = 1). (4) tmstp+/ ? does not have internal biasing which requires tmstp+/ ? to be biased externally whether ac coupled with tmstp_lvpecl_en = 0 or dc coupled with tmstp_lvpecl_en = 1. (5) adc output code will saturate when v id for ina+/ ? or inb+/ ? exceeds the programmed full-scale voltage (v fs ) set by fs_range_a for ina+/ ? or fs_range_b for inb+/ ? . (6) prolonged use above this junction temperature may increase the device failure-in-time (fit) rate. (7) tested up to 1000 hours continuous operation at t j = 125 c. see absolute maximum ratings for absolute maximum operational temperature. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v dd supply voltage range va19, analog 1.9v supply (1) 1.8 1.9 2.0 v va11, analog 1.1v supply (1) 1.05 1.1 1.15 v vd11, digital 1.1v supply (2) 1.05 1.1 1.15 v v cmi input common mode voltage ina+, ina ? , inb+, inb ? (1) -50 0 100 mv clk+, clk ? , sysref+, sysref ? (1) (3) 0.0 0.3 0.55 v tmstp+, tmstp ? (1) (4) 0.0 0.3 0.55 v v id input voltage, peak-to-peak differential clk+ to clk ? , sysref+ to sysref ? , tmstp+ to tmstp ? 0.4 1.0 2.0 v pp-diff ina+ to ina ? , inb+ to inb ? 1.0 (5) v pp-diff v ih high level input voltage caltrig, ncoa0, ncoa1, ncob0, ncob1, pd, sclk, scs, sdi, syncse (1) 0.7 v v il low level input voltage caltrig, ncoa0, ncoa1, ncob0, ncob1, pd, sclk, scs, sdi, syncse (1) 0.45 v i c_td temperature diode input current tdiode+ to tdiode ? 100 a c l bg max load capacitance 50 pf i o bg max output current 100 a dc input clock duty cycle 30 50 70 % t a operating free-air temperature -40 85 o c t j operating junction temperature 105 (6) (7) o c
11 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. note power down of the high speed data outputs (da0+/ ? ... da7+/ ? , db0+/ ? ... db7+/ ? ) for extended times may reduce performance of the output serializers, especially at high data rates. power down of the serializers occurs when the pd pin is held high, the mode register is programmed to a value other than 0x00 or 0x01, pd_ach or pd_bch registers settings are programmed to 1 or when the jmode register setting is programmed to a mode that uses less than the 16 total lanes the device allows. for instance, jmode 0 uses eight total lanes and therefore the four highest indexed lanes for each jesd204b link (da4+/ ? ... da7+/ ? , db4+/ ? ... db7+/ ? ) are powered down in this mode. when the pd pin is held high or the mode register is programmed to a value other than 0x00 or 0x01 then all of the output serializers are powered down. when pd_ach or pd_bch register settings are programmed to 1 the associated adc channel and lanes are powered down. to prevent unreliable operation the pd pin and mode register should only be used for brief periods of time to measure temperature diode offsets and not used for long-term power savings. further, use of a jmode that uses fewer than 16 lanes will result in unreliable operation of the unused lanes. if the system will never use the unused lanes during the lifetime of the device then the unused lanes will not cause issues and can be powered down. if the system may make use of the unused lanes at a later time, the reliable operation of the serializer outputs can be maintained by enabling jextra_a and jextra_b which results in vd11 power consumption to increase and the output serializers to toggle. 6.4 thermal information thermal metric (1) adc12dj3200 unit aav (fcbga) 144 pins r ja junction-to-ambient thermal resistance 25.3 c/w r jc(top) junction-to-case (top) thermal resistance 1.1 c/w r jb junction-to-board thermal resistance 8.2 c/w jt junction-to-top characterization parameter 0.1 c/w jb junction-to-board characterization parameter 8.2 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w
12 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.5 electrical characteristics - dc specifications typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit dc accuracy resolution resolution with no missing codes 12 bits dnl differential nonlinearity 0.3 lsb inl integral nonlinearity 2.5 lsb analog inputs (ina+, ina ? , inb+, inb ? ) v off offset error default full-scale voltage, os_cal disabled 0.6 mv v off_adj input offset voltage adjustment range available offset correction range (see os_cal or oadj_x_inx) 55 mv v off_drift offset drift foreground calibration at nominal temperature only 23 v/ c foreground calibration at each temperature 0 v/ c v in_fsr analog differential input full scale range default full-scale voltage (fs_range_a = fs_range_b = 0xa000) 750 800 850 mv pp maximum full-scale voltage (fs_range_a = fs_range_b = 0xffff) 1000 1040 mv pp minimum full-scale voltage (fs_range_a = fs_range_b = 0x2000) 480 500 mv pp v in_fsr_drift analog differential input full scale range drift default fs_range_a and fs_range_b setting, foreground calibration at nominal temperature only, inputs driven by 50- source, includes effect of r in drift -0.01 %/ c default fs_range_a and fs_range_b setting, foreground calibration at each temperature, inputs driven by 50- source, includes effect of r in drift 0.03 %/ c v in_fsr_match analog differential input full scale range matching matching between ina+/ina ? and inb+/inb ? , default setting, dual channel mode 0.625 % r in single-ended input resistance to agnd each input terminal is terminated to agnd, measured at t a = 25 c 48 50 52 r in_tempco input termination linear temperature coefficient 17.6 m / c c in single-ended input capacitance single channel mode at dc 0.4 pf dual channel mode at dc 0.4 pf temperature diode characteristics (tdiode+, tdiode ? ) v be temperature diode voltage slope forced forward current of 100 a. offset voltage (approx. 0.792 v at 0 c) varies with process and must be measured for each part. offset measurement should be done with the device unpowered or with the pd pin asserted to minimize device self-heating. pd pin should be asserted only long enough to take the offset measurement. -1.6 mv/ c bandgap voltage output (bg) v bg reference output voltage i l 100 a 1.1 v v bg_drift reference output temperature drift i l 100 a -64 v/ c
13 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - dc specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit clock inputs (clk+, clk ? , sysref+, sysref ? , tmstp+, tmstp ? ) z t internal termination differential termination with devclk_lvpecl_en = 0, sysref_lvpecl_en = 0 and tmstp_lvpecl_en = 0 110 single ended termination to gnd (per pin) with devclk_lvpecl_en = 0, sysref_lvpecl_en = 0 and tmstp_lvpecl_en = 0 55 v cm input common mode voltage, self-biased self-biasing common mode voltage for clk+/ ? when ac coupled (devclk_lvpecl_en must be set to 0) 0.26 v self-biasing common mode voltage for sysref+/ ? when ac coupled (sysref_lvpecl_en must be set to 0) and with receiver enabled (sysref_recv_en = 1). 0.29 v self-biasing common mode voltage for sysref+/ ? when ac coupled (sysref_lvpecl_en must be set to 0) and with receiver disabled (sysref_recv_en = 0). va11 v c l_diff differential input capacitance between positive and negative differential input pins 0.1 pf c l_se single-ended input capacitance each input to ground 0.5 pf serdes outputs (da0+/da0 ? ...da7+/da7 ? , db0+/db0 ? ...db7+/db7 ? ) v od differential output voltage, peak-to-peak 100- load 550 600 650 mv pp- diff v cm output common mode voltage ac coupled vd11/2 v z diff differential output impedance 100 cmos interface: sclk, sdi, sdo, scs, pd, ncoa0, ncoa1, ncob0, ncob1, calstat, caltrig, ora0, ora1, orb0, orb1, syncse i ih high level input current ? 40 40 a i il low level input current ? 40 40 a c i input capacitance 2 pf v oh high level output voltage i load = ? 400 a 1.65 v v ol low level output voltage i load = 400 a 150 mv
14 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.6 electrical characteristics - power consumption typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit i va19 1.9-v analog supply current power mode 1: single channel mode, jmode 1 (16 lanes, ddc bypassed), foreground calibration 897 ma i va11 1.1-v analog supply current 491 ma i vd11 1.1-v digital supply current 640 ma p dis power dissipation 3.0 w i va19 1.9-v analog supply current power mode 2: single channel mode, jmode 0 (8 lanes, ddc bypassed), foreground calibration 875 950 ma i va11 1.1-v analog supply current 515 600 ma i vd11 1.1-v digital supply current 615 750 ma p dis power dissipation 2.9 3.5 w i va19 1.9-v analog supply current power mode 3: single channel mode, jmode 1 (16 lanes, ddc bypassed), background calibration 1181 ma i va11 1.1-v analog supply current 595 ma i vd11 1.1-v digital supply current 653 ma p dis power dissipation 3.6 w i va19 1.9-v analog supply current power mode 4: dual channel mode, jmode 3 (16 lanes, ddc bypassed), background calibration 1260 ma i va11 1.1-v analog supply current 594 ma i vd11 1.1-v digital supply current 636 ma p dis power dissipation 3.8 w i va19 1.9-v analog supply current power mode 5: dual channel mode, jmode 11 (8 lanes, 4x decimation), foreground calibration 964 ma i va11 1.1-v analog supply current 493 ma i vd11 1.1-v digital supply current 802 ma p dis power dissipation 3.3 w
15 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) full-power input bandwidth (fpbw) is defined as the input frequency where the reconstructed output of the adc has dropped 3 db below the power of a full-scale input signal at a low input frequency. useable bandwidth may exceed the -3-db full-power input bandwidth. 6.7 electrical characteristics - ac specifications typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit analog inputs (ina+, ina ? , inb+, inb ? ) fpbw full-power input bandwidth ( ? 3 db) (1) dual channel mode, foreground calibration 8.1 ghz single channel mode, foreground calibration 7.9 dual channel mode, background calibration 8.1 single channel mode, background calibration 7.9 xtalk channel-to-channel crosstalk dual channel mode, aggressor = 400 mhz, ? 1 dbfs ? 93 db dual channel mode, aggressor = 3 ghz, ? 1 dbfs ? 70 dual channel mode, aggressor = 6 ghz, ? 1 dbfs ? 63 dynamic ac characteristics - dual channel mode (jmode 3) cer code error rate 10 ? 18 errors/sam ple noise dc dc input noise standard deviation no input, foreground calibration, excludes dc offset, includes fixed interleaving spur (fs/2 spur) 2 lsb nsd noise spectral density, no input signal, excludes fixed interleaving spur (fs/2 spur) maximum full-scale voltage (fs_range_a = fs_range_b = 0xffff) setting, foreground calibration -151.8 dbfs/hz default full-scale voltage (fs_range_a = fs_range_b = 0xa000) setting, foreground calibration -150.2 nf noise figure, no input, z s = 100 maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration 23.5 db default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration 22.8 snr signal to noise ratio, large signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 1 dbfs 56.6 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 57.6 f in = 997 mhz, a in = ? 1 dbfs 56.3 f in = 2482 mhz, a in = ? 1 dbfs 52 55.2 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 56.1 f in = 4997 mhz, a in = ? 1 dbfs 52.6 f in = 6397 mhz, a in = ? 1 dbfs 51.3 f in = 8197 mhz, a in = ? 1 dbfs 49.8
16 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit snr signal to noise ratio, small signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 16 dbfs 57.4 dbfs f in = 997 mhz, a in = ? 16 dbfs 57.5 f in = 2482 mhz, a in = ? 16 dbfs 57.4 f in = 4997 mhz, a in = ? 16 dbfs 57.1 f in = 6397 mhz, a in = ? 16 dbfs 57.3 f in = 8197 mhz, a in = ? 16 dbfs 56.9 sinad signal to noise and distortion ratio, large signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 56.0 dbfs f in = 997 mhz, a in = ? 1 dbfs 55.7 f in = 2482 mhz, a in = ? 1 dbfs 51 54.6 f in = 4997 mhz, a in = ? 1 dbfs 50.3 f in = 6397 mhz, a in = ? 1 dbfs 48.9 f in = 8197 mhz, a in = ? 1 dbfs 47.4 enob effective number of bits, large signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 9.0 bits f in = 997 mhz, a in = ? 1 dbfs 9.0 f in = 2482 mhz, a in = ? 1 dbfs 8.2 8.8 f in = 4997 mhz, a in = ? 1 dbfs 8.1 f in = 6397 mhz, a in = ? 1 dbfs 7.8 f in = 8197 mhz, a in = ? 1 dbfs 7.6 sfdr spurious free dynamic range, large signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 67 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 67 f in = 997 mhz, a in = ? 1 dbfs 69 f in = 2482 mhz, a in = ? 1 dbfs 60 66 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration 63 f in = 4997 mhz, a in = ? 1 dbfs 56 f in = 6397 mhz, a in = ? 1 dbfs 55 f in = 8197 mhz, a in = ? 1 dbfs 52 sfdr spurious free dynamic range, small signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 16 dbfs 73 dbfs f in = 997 mhz, a in = ? 16 dbfs 72 f in = 2482 mhz, a in = ? 16 dbfs 72 f in = 4997 mhz, a in = ? 16 dbfs 72 f in = 6397 mhz, a in = ? 16 dbfs 72 f in = 8197 mhz, a in = ? 16 dbfs 72 f s /2 f s /2 fixed interleaving spur, independent of input signal no input ? 75 ? 55 dbfs
17 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit hd2 2 nd order harmonic f in = 347 mhz, a in = ? 1 dbfs ? 73 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 72 f in = 997 mhz, a in = ? 1 dbfs ? 72 f in = 2482 mhz, a in = ? 1 dbfs ? 67 ? 60 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 66 f in = 4997 mhz, a in = ? 1 dbfs ? 58 f in = 6397 mhz, a in = ? 1 dbfs ? 57 f in = 8197 mhz, a in = ? 1 dbfs ? 58 hd3 3 rd order harmonic f in = 347 mhz, a in = ? 1 dbfs ? 70 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 68 f in = 997 mhz, a in = ? 1 dbfs ? 72 f in = 2482 mhz, a in = ? 1 dbfs ? 69 ? 60 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a and fs_range_b setting, foreground calibration ? 63 f in = 4997 mhz, a in = ? 1 dbfs ? 57 f in = 6397 mhz, a in = ? 1 dbfs ? 55 f in = 8197 mhz, a in = ? 1 dbfs ? 52 f s /2-f in f s /2-f in interleaving spur, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 69 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 70 f in = 2482 mhz, a in = ? 1 dbfs ? 70 ? 60 f in = 4997 mhz, a in = ? 1 dbfs ? 67 f in = 6397 mhz, a in = ? 1 dbfs ? 63 f in = 8197 mhz, a in = ? 1 dbfs ? 63 spur worst harmonic 4 th order or higher f in = 347 mhz, a in = ? 1 dbfs ? 72 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 72 f in = 2482 mhz, a in = ? 1 dbfs ? 73 ? 65 f in = 4997 mhz, a in = ? 1 dbfs ? 70 f in = 6397 mhz, a in = ? 1 dbfs ? 69 f in = 8197 mhz, a in = ? 1 dbfs ? 67
18 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit imd3 3 rd order intermodulation f in = 347 mhz 5 mhz, a in = ? 7 dbfs per tone ? 81 dbfs f in = 997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 78 f in = 2482 mhz 5 mhz, a in = ? 7 dbfs per tone ? 73 f in = 4997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 65 f in = 6397 mhz 5 mhz, a in = ? 7 dbfs per tone ? 56 f in = 8197 mhz 5 mhz, a in = ? 7 dbfs per tone ? 46
19 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit dynamic ac characteristics - single channel mode (jmode 1) cer code error rate 10 ? 18 errors/sam ple noise dc dc input noise standard deviation no input, foreground calibration, excludes dc offset, includes fixed interleaving spurs (fs/2 and fs/4 spurs) 3.5 lsb nsd noise spectral density, no input signal, excludes fixed interleaving spurs (fs/2 and fs/4 spur) maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration -154.6 dbfs/hz default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration -153.1 nf noise figure, no input, z s = 100 maximum full-scale voltage (fs_range_a = 0xffff) setting, foreground calibration 20.7 db default full-scale voltage (fs_range_a = 0xa000) setting, foreground calibration 19.9 snr signal to noise ratio, large signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 1 dbfs 56.6 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 57.5 f in = 997 mhz, a in = ? 1 dbfs 56.3 f in = 2482 mhz, a in = ? 1 dbfs 52 55.3 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 56.1 f in = 4997 mhz, a in = ? 1 dbfs 53.0 f in = 6397 mhz, a in = ? 1 dbfs 51.6 f in = 8197 mhz, a in = ? 1 dbfs 50.0 snr signal to noise ratio, small signal, excluding dc, hd2 to hd9 and interleaving spurs f in = 347 mhz, a in = ? 16 dbfs 57.4 dbfs f in = 997 mhz, a in = ? 16 dbfs 57.6 f in = 2482 mhz, a in = ? 16 dbfs 57.4 f in = 4997 mhz, a in = ? 16 dbfs 57.3 f in = 6397 mhz, a in = ? 16 dbfs 57.4 f in = 8197 mhz, a in = ? 16 dbfs 57.0 sinad signal to noise and distortion ratio, large signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 52.7 dbfs f in = 997 mhz, a in = ? 1 dbfs 52.4 f in = 2482 mhz, a in = ? 1 dbfs 48 52.1 f in = 4997 mhz, a in = ? 1 dbfs 47.5 f in = 6397 mhz, a in = ? 1 dbfs 46.6 f in = 8197 mhz, a in = ? 1 dbfs 47.7
20 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit enob effective number of bits, large signal, excluding dc and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 8.6 dbfs f in = 997 mhz, a in = ? 1 dbfs 8.5 f in = 2482 mhz, a in = ? 1 dbfs 7.7 8.4 f in = 4997 mhz, a in = ? 1 dbfs 7.7 f in = 6397 mhz, a in = ? 1 dbfs 7.5 f in = 8197 mhz, a in = ? 1 dbfs 7.6 sfdr spurious free dynamic range, large signal, excluding dc, f s /4 and f s /2 fixed spurs f in = 347 mhz, a in = ? 1 dbfs 67 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 64 f in = 997 mhz, a in = ? 1 dbfs 63 f in = 2482 mhz, a in = ? 1 dbfs 50 58 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration 55 f in = 4997 mhz, a in = ? 1 dbfs 51 f in = 6397 mhz, a in = ? 1 dbfs 50 f in = 8197 mhz, a in = ? 1 dbfs 48 sfdr spurious free dynamic range, small signal, excluding dc, f s /4 and f s /2 fixed spurs f in = 347 mhz, a in = ? 16 dbfs 75 dbfs f in = 997 mhz, a in = ? 16 dbfs 73 f in = 2482 mhz, a in = ? 16 dbfs 72 f in = 4997 mhz, a in = ? 16 dbfs 66 f in = 6397 mhz, a in = ? 16 dbfs 65 f in = 8197 mhz, a in = ? 16 dbfs 63 f s /2 f s /2 fixed interleaving spur, independent of input signal no input, os_cal disabled. spur can be improved by running os_cal. ? 56 dbfs f s /4 f s /4 fixed interleaving spur, independent of input signal no input ? 65 ? 55 dbfs hd2 2 nd order harmonic f in = 347 mhz, a in = ? 1 dbfs ? 73 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 76 f in = 997 mhz, a in = ? 1 dbfs ? 74 f in = 2482 mhz, a in = ? 1 dbfs ? 68 ? 60 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 72 f in = 4997 mhz, a in = ? 1 dbfs ? 62 f in = 6397 mhz, a in = ? 1 dbfs ? 62 f in = 8197 mhz, a in = ? 1 dbfs ? 61
21 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit hd3 3 rd order harmonic f in = 347 mhz, a in = ? 1 dbfs ? 70 dbfs f in = 347 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 68 f in = 997 mhz, a in = ? 1 dbfs ? 68 f in = 2482 mhz, a in = ? 1 dbfs ? 69 ? 60 f in = 2482 mhz, a in = ? 1 dbfs, maximum fs_range_a setting, foreground calibration ? 64 f in = 4997 mhz, a in = ? 1 dbfs ? 59 f in = 6397 mhz, a in = ? 1 dbfs ? 58 f in = 8197 mhz, a in = ? 1 dbfs ? 55 f s /2-f in f s /2-f in interleaving spur, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 68 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 63 f in = 2482 mhz, a in = ? 1 dbfs ? 58 ? 50 f in = 4997 mhz, a in = ? 1 dbfs ? 51 f in = 6397 mhz, a in = ? 1 dbfs ? 50 f in = 8197 mhz, a in = ? 1 dbfs ? 48 f s /4 f in f s /4 f in interleaving spurs, signal dependent f in = 347 mhz, a in = ? 1 dbfs ? 74 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 69 f in = 2482 mhz, a in = ? 1 dbfs ? 70 ? 60 f in = 4997 mhz, a in = ? 1 dbfs ? 66 f in = 6397 mhz, a in = ? 1 dbfs ? 63 f in = 8197 mhz, a in = ? 1 dbfs ? 61 spur worst harmonic 4 th order or higher f in = 347 mhz, a in = ? 1 dbfs ? 73 dbfs f in = 997 mhz, a in = ? 1 dbfs ? 73 f in = 2482 mhz, a in = ? 1 dbfs ? 75 ? 65 f in = 4997 mhz, a in = ? 1 dbfs ? 69 f in = 6397 mhz, a in = ? 1 dbfs ? 69 f in = 8197 mhz, a in = ? 1 dbfs ? 63 imd3 3 rd order intermodulation f in = 347 mhz 5 mhz, a in = ? 7 dbfs per tone ? 80 dbfs f in = 997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 75 f in = 2482 mhz 5 mhz, a in = ? 7 dbfs per tone ? 72 f in = 4997 mhz 5 mhz, a in = ? 7 dbfs per tone ? 63 f in = 6397 mhz 5 mhz, a in = ? 7 dbfs per tone ? 65 f in = 8197 mhz 5 mhz, a in = ? 7 dbfs per tone ? 50
22 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) unless functionally limited to a smaller range in table 18 based on programmed jmode. (2) sysref_pos should be used to select an optimal sysref_sel value for sysref capture, see sysref position detector and sampling position selection (sysref windowing) for more information on sysref windowing. the invalid region, specified by t inv(sysref) , indicates the portion of the clk+/ ? period (t clk ), as measured by sysref_sel, that may result in a setup and hold violation. the user should verify that the timing skew between sysref+/ ? and clk+/ ? over system operating conditions from the nominal conditions (that used to find optimal sysref_sel) does not result in the invalid region occurring at the selected sysref_sel position in sysref_pos, otherwise a temperature dependent sysref_sel selection may be needed to track the skew between clk+/ ? and sysref+/ ? . 6.8 timing requirements min nom max unit device (sampling) clock (clk+, clk ? ) f clk input clock frequency (clk+, clk ? ), both single channel and dual channel modes (1) 800 3200 mhz sysref (sysref+, sysref ? ) t inv(sysref) width of invalid sysref capture region of clk+/ ? period, indicating setup or hold time violation, as measured by sysref_pos status register (2) 48 ps t inv(temp) drift of invalid sysref capture region over temperature, positive number indicates a shift toward msb of sysref_pos register 0 ps/ c t inv(va11) drift of invalid sysref capture region over va11 supply voltage, positive number indicates a shift toward msb of sysref_pos register 0.36 ps/mv t step(sp) delay of sysref_pos lsb sysref_zoom = 0 77 ps sysref_zoom = 1 24 ps t (ph_sys) minimum sysref+/ ? assertion duration after sysref+/ ? rising edge event 4 ns t (pl_sys) minimum sysref+/ ? deassertion duration after sysref+/ ? falling edge event 1 ns jesd204b sync timing ( syncse or tmstp+/ ? ) t h( syncse) minimum hold time from multi-frame boundary (sysref rising edge captured high) to de- assertion of jesd204b sync signal ( syncse if sync_sel = 0 or tmstp+/ ? if sync_sel = 1) for nco synchronization (nco_sync_ila = 1) jmode = 0, 2, 4, 6, 10, 13 or 15 21 t clk cycles jmode = 1, 3, 5, 7, 9, 11, 14 or 16 17 jmode = 12, 17 or 18 9 t su( syncse) minimum setup time from de-assertion of jesd204b sync signal ( syncse if sync_sel = 0 or tmstp+/ ? if sync_sel = 1) to multi- frame boundary (sysref rising edge captured high) for nco synchronization (nco_sync_ila = 1) jmode = 0, 2, 4, 6, 10, 13 or 15 ? 2 t clk cycles jmode = 1, 3, 5, 7, 9, 11, 14 or 16 2 jmode = 12, 17 or 18 10 t ( syncse) syncse minimum assertion time to trigger link resynchronization 4 frames serial programming interface (sclk, sdi, scs) f clk(sclk) maximum serial clock frequency 15.625 mhz t (ph) minimum serial clock high value pulse width 32 ns t (pl) minimum serial clock low value pulse width 32 ns t su( scs) minimum setup time from scs to rising edge of sclk 30 ns t h( scs) minimum hold time from rising edge of sclk to scs 3 ns t su(sdi) minimum setup time from sdi to rising edge of sclk 30 ns t h(sdi) minimum hold time from rising edge of sclk to sdi 3 ns
23 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) t aj increases due to additional attenuation on internal clock path. 6.9 switching characteristics typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit device (sampling) clock (clk+, clk ? ) t ad sampling (aperture) delay from clk+/- rising edge (dual channel mode) or rising and falling edge (single channel mode) to sampling instant tad_coarse = 0x00, tad_fine = 0x00 and tad_inv = 0 360 ps t tad(max) maximum t ad adjust programmable delay, not including clock inversion (tad_inv = 0) coarse adjustment (tad_coarse = 0xff) 289 ps fine adjustment (tad_fine = 0xff) 4.9 ps t tad(step) t ad adjust programmable delay step size coarse adjustment (tad_coarse) 1.13 ps fine adjustment (tad_fine) 19 fs t aj aperture jitter, rms minimum t ad adjust coarse setting (tad_coarse = 0x00, tad_inv = 0) 50 fs maximum t ad adjust coarse setting (tad_coarse = 0xff) excluding tad_inv (tad_inv = 0) 70 (1) fs serial data outputs (da0+...da7+, da0 ? ...da7 ? , db0+...db7+, db0 ? ...db7 ? ) f serdes serialized output bit rate 1 12.8 gbps ui serialized output unit interval 78.125 1000 ps t tlh low-to-high transition time (differential) 20% to 80%, prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04 37 ps t thl high-to-low transition time (differential) 20% to 80%, prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04 37 ps ddj data dependent jitter, peak-to-peak prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 2 7.8 ps rj random jitter, rms prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 2 1.1 ps tj total jitter, peak-to-peak, with gaussian portion defined with respect to a ber=1e-15 (q=7.94) prbs-7 test pattern, 12.8 gbps, ser_pe = 0x04, jmode = 0, 2 25 ps prbs-7 test pattern, 6.4 gbps, ser_pe = 0x04, jmode = 1, 3 21 ps prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 4, 5, 6, 7 28 ps prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 9 35 ps prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 10, 11 40 ps prbs-7 test pattern, 3.2 gbps, ser_pe = 0x04, jmode = 12 26 ps prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 13, 14 39 ps prbs-7 test pattern, 8 gbps, ser_pe = 0x04, jmode = 15, 16 34 ps
24 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated switching characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit (2) t adc is an exact, unrounded, deterministic delay. the delay can be negative if the reference sample is sampled after the sysref high capture point, in which case the total latency is smaller than the delay given by t tx . (3) the values given for t tx include deterministic and non-deterministic delays. over process, temperature, and voltage, the delay will vary. jesd204b accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. proper receiver rbd value must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multi-frame clock (lmfc) cycle. adc core latency t adc deterministic delay from the clk+/ ? edge that samples the reference sample to the clk+/ ? edge that samples sysref going high (2) jmode = 0 -8.5 t clk cycles jmode = 1 -20.5 jmode = 2 -9 jmode = 3 -21 jmode = 4 -4.5 jmode = 5 -24.5 jmode = 6 -5 jmode = 7 -25 jmode = 9 60 jmode = 10 140 jmode = 11 136 jmode = 12 120 jmode = 13 232 jmode = 14 232 jmode = 15 446 jmode = 16 430 jmode = 17 -48.5 jmode = 18 -49 jesd204b and serializer latency t tx delay from the clk+/ ? rising edge that samples sysref high to the first bit of the multi-frame on the jesd204b serial output lane corresponding to the reference sample of t adc (3) jmode = 0 72 84 t clk cycles jmode = 1 119 132 jmode = 2 72 84 jmode = 3 119 132 jmode = 4 67 80 jmode = 5 106 119 jmode = 6 67 80 jmode = 7 106 119 jmode = 9 106 119 jmode = 10 67 80 jmode = 11 106 119 jmode = 12 213 225 jmode = 13 67 80 jmode = 14 106 119 jmode = 15 67 80 jmode = 16 106 119 jmode = 17 195 208 jmode = 18 195 208
25 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated switching characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = 1.1v, vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/ ? in single channel modes, f in = 248 mhz, a in = ? 1 dbfs, f clk = maximum rated clock frequency, filtered 1-vpp sine-wave clock, jmode = 1, background calibration, unless otherwise noted. minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in recommended operating conditions . parameter test conditions min typ max unit serial programming interface (sdo) t (ozd) maximum delay from falling edge of 16th sclk cycle during read operation for sdo transition from tri-state to valid data 7 ns t (odz) maximum delay from scs rising edge for sdo transition from valid data to tri-state 7 ns t (od) maximum delay from falling edge of 16th sclk cycle during read operation to sdo valid 12 ns figure 1. adc timing diagram figure 2. syncse and tmstp+/ ? timing diagram for nco synchronization clk+ clk da0+/ (2) sysref+ sysref /r (1) it is assumed that the internal lmfc is aligned with the rising edge of clk+/- that captures sysref+/- high value. (2) only serdes lane da0+/- is shown, but it is representative of all lanes. all lanes will output /r at approximately the same point in time. number of lanes is dependent on the programmed jmode value. syncse (sync_sel=0) t h(syncse) t su(syncse) t tx start of ilas lmfc (1) (internal) one multi-frame one multi-frame tmstp+/ (sync_sel=1) clk+ clk da0+/ * t ad t adc sysref+ sysref t su(sysref) t tx s 0 s 1 s 2 t clk s 0 s 1 s 2 * only serdes lane da0+/- is shown, but it is representative of all lanes. the number of output lanes used and bit-packin g format is dependent on the programmed jmode value. t h(sysref) start of multi-frame
26 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 3. serial interface timing t h(scs) 1 st clock sclk 16 th clock 24 th clock scs t su(scs) t (odz) sdi t (ozd) d7 d0 d1 command field t (od) d7 d0 d1 sdo write command read command t su(sdi) t h(sdi) t (ph) t (pl) t (ph) + t (pl) = t (p) = 1 / | clk(sclk) hi-z hi-z t h(scs) t su(scs) t su(sdi) t h(sdi)
27 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.10 typical characteristics typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode3 f clk = 3200 mhz fg calibration figure 4. enob vs input frequency jmode3 f clk = 3200 mhz fg calibration figure 5. snr, sinad, sfdr vs input frequency jmode1 f clk = 3200 mhz fg+bg calibration figure 6. enob vs input frequency jmode1 f clk = 3200 mhz fg calibration figure 7. snr, sinad, sfdr vs input frequency jmode1 f clk = 3200 mhz fg calibration figure 8. h2, h3, thd vs input frequency jmode1 f in = 347 mhz fg calibration figure 9. power consumption vs clock frequency fin (mhz) enob (bits) 0 2000 4000 6000 8000 10000 7.25 7.5 7.75 8 8.25 8.5 8.75 9 9.25 d132 fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 40 45 50 55 60 65 70 75 d131 snr (dbfs) sinad (dbfs) sfdr (dbfs) fin (mhz) enob (bits) 0 2000 4000 6000 8000 10000 7 7.25 7.5 7.75 8 8.25 8.5 8.75 9 d002 bg calibration fg calibration fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 40 45 50 55 60 65 70 75 d129 snr (dbfs) sinad (dbfs) sfdr (dbfs) fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 d130 h2 (dbfs) h3 (dbfs) thd (dbfs) fclk (mhz) power consumption (w) 800 1200 1600 2000 2400 2800 3200 2 2.2 2.4 2.6 2.8 3 3.2 d008
28 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode1 f in = 2400 mhz figure 10. enob vs temperature jmode1 f in = 600 mhz f clk = 3200 mhz figure 11. enob vs temperature and calibration type jmode1 f in = 600 mhz f clk = 3200 mhz figure 12. snr vs temperature and calibration type jmode1 f in = 600 mhz f clk = 3200 mhz figure 13. sfdr vs temperature and calibration type jmode1 f in = 600 mhz f clk = 3200 mhz figure 14. h2 vs temperature and calibration type jmode1 f in = 600 mhz f clk = 3200 mhz figure 15. h3 vs temperature and calibration type ambient temperature (c) enob (bits) -75 -50 -25 0 25 50 75 100 125 8 8.25 8.5 8.75 9 d040 bg calibration fg calibration each temperature ambient temperature (c) enob (bits) -75 -50 -25 0 25 50 75 100 125 7 7.5 8 8.5 9 d121 fg calibration each temperature fg calibration at 25c ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 52 56 60 64 68 72 d064 fg calibration each temperature fg calibration at 25c ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 48 50 52 54 56 58 60 d063 fg calibration each temperature fg calibration at 25c ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 -90 -85 -80 -75 -70 -65 -60 -55 d120 fg calibration each temperature fg calibration at 25c ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 -90 -85 -80 -75 -70 -65 -60 -55 d119 fg calibration each temperature fg calibration at 25c
29 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode1 f clk = 3200 mhz bg calibration figure 16. snr, sinad, sfdr vs input frequency jmode1 f clk = 3200 mhz bg calibration figure 17. h2, h3, thd vs input frequency jmode1 f in = 347 mhz bg calibration figure 18. snr, sinad, sfdr vs clock frequency jmode1 f in = 347 mhz bg calibration figure 19. enob vs clock frequency jmode1 f in = 347 mhz bg calibration figure 20. h2, h3, thd vs clock frequency jmode1 f in = 347 mhz fg calibration figure 21. supply current vs clock frequency fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 40 45 50 55 60 65 70 75 d001 snr (dbfs) sinad (dbfs) sfdr (dbfs) fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 d003 h2 (dbfs) h3 (dbfs) thd (dbfs) fclk (mhz) magnitude (dbfs) 800 1200 1600 2000 2400 2800 3200 -90 -85 -80 -75 -70 -65 -60 -55 d006 h2 (dbfs) h3 (dbfs) thd (dbfs) fclk (mhz) magnitude (dbfs) 800 1200 1600 2000 2400 2800 3200 40 45 50 55 60 65 70 75 d004 snr (dbfs) sinad (dbfs) sfdr (dbfs) fclk (mhz) supply current (a) 800 1200 1600 2000 2400 2800 3200 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 d007 ia19 ia11 id11 fclk (mhz) enob (bits) 800 1200 1600 2000 2400 2800 3200 7 7.25 7.5 7.75 8 8.25 8.5 8.75 9 d005
30 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode3 f clk = 3200 mhz bg calibration figure 22. snr, sinad, sfdr vs input frequency jmode3 f clk = 3200 mhz bg calibration figure 23. enob vs input frequency jmode3 f clk = 3200 mhz bg calibration figure 24. h2, h3, thd vs input frequency jmode3 f in = 347 mhz bg calibration figure 25. snr, sinad, sfdr vs clock frequency jmode3 f in = 347 mhz bg calibration figure 26. enob vs clock frequency jmode3 f in = 347 mhz bg calibration figure 27. h2, h3, thd vs clock frequency fclk (mhz) enob (bits) 800 1200 1600 2000 2400 2800 3200 8.5 8.75 9 9.25 9.5 d013 fclk (mhz) magnitude (dbfs) 800 1200 1600 2000 2400 2800 3200 -90 -85 -80 -75 -70 -65 -60 -55 d014 h2 (dbfs) h3 (dbfs) thd (dbfs) fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 d011 h2 (dbfs) h3 (dbfs) thd (dbfs) fclk (mhz) magnitude (dbfs) 800 1200 1600 2000 2400 2800 3200 40 45 50 55 60 65 70 75 d012 snr (dbfs) sinad (dbfs) sfdr (dbfs) fin (mhz) enob (bits) 0 2000 4000 6000 8000 10000 7.25 7.5 7.75 8 8.25 8.5 8.75 9 9.25 d010 fin (mhz) magnitude (dbfs) 0 2000 4000 6000 8000 10000 40 45 50 55 60 65 70 75 d009 snr (dbfs) sinad (dbfs) sfdr (dbfs)
31 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode3 f in = 347 mhz fg calibration figure 28. supply current vs clock frequency jmode3 f in = 347 mhz fg calibration figure 29. power consumption vs clock frequency jmode1 f in = 2400 mhz bg calibration figure 30. snr, sinad, sfdr vs temperature jmode1 f in = 2400 mhz bg calibration figure 31. h2, h3, thd vs temperature jmode1 f in = 600 mhz fg calibration figure 32. snr sinad sfdr vs supply voltage jmode1 f in = 600 mhz fg calibration figure 33. enob vs supply voltage ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 -90 -85 -80 -75 -70 -65 -60 -55 d041 h2 (dbfs) h3 (dbfs) thd (dbfs) fclk (mhz) supply current (a) 800 1200 1600 2000 2400 2800 3200 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 d015 ia19 ia11 id11 ambient temperature (c) magnitude (dbfs) -75 -50 -25 0 25 50 75 100 125 40 45 50 55 60 65 70 75 d039 snr (dbfs) sinad (dbfs) sfdr (dbfs) fclk (mhz) power consumption (w) 800 1200 1600 2000 2400 2800 3200 2 2.2 2.4 2.6 2.8 3 3.2 d016 supply voltage (%) enob (bits) -5 -2.5 0 2.5 5 9 9.2 9.4 9.6 9.8 d037 supply voltage (%) magnitude (dbfs) -5 -2.5 0 2.5 5 50 52 54 56 58 60 d036 snr (dbfs) sinad (dbfs) sfdr (dbfs)
32 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode1 f in = 600 mhz fg calibration figure 34. h2, h3, thd vs supply voltage jmode1 f in = 2400 mhz bg calibration figure 35. supply current vs temperature jmode1 f in = 2400 mhz bg calibration figure 36. power consumption vs temperature jmode1 f clk = 3200 mhz fg calibration figure 37. supply current vs supply voltage jmode1 f clk = 3200 mhz fg calibration figure 38. power consumption vs supply voltage jmode0 f in = 607 mhz figure 39. ia19 vs clock frequency fclk (mhz) supply current (a) 800 1200 1600 2000 2400 2800 3200 0.7 0.8 0.9 1 1.1 1.2 d123 bg calibration fg calibration lpbg calibration ambient temperature (c) power consumption (w) -75 -50 -25 0 25 50 75 100 125 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 d046 bg calibration fg calibration supply voltage (%) power consumption (w) -5 -2.5 0 2.5 5 2.4 2.6 2.8 3 3.2 d044 supply voltage (%) magnitude (dbfs) -5 -2.5 0 2.5 5 -90 -85 -80 -75 -70 -65 -60 -55 d038 h2 (dbfs) h3 (dbfs) thd (dbfs) supply voltage (%) supply current (a) -5 -2.5 0 2.5 5 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d045 ia19 ia11 id11 ambient temperature (c) supply current (a) -75 -50 -25 0 25 50 75 100 125 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 d047 ia19 ia11 id11
33 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode0 f in = 607 mhz figure 40. ia11 vs clock frequency jmode0 f in = 607 mhz figure 41. id11 vs clock frequency jmode0 f in = 607 mhz figure 42. power consumption vs clock frequency f clk = 3200 mhz f in = 2400 mhz fg calibration figure 43. snr, sinad, sfdr vs decimation factor f clk = 3200 mhz fg calibration figure 44. enob vs decimation factor f in = 2400 mhz f clk = 3200 mhz fg calibration figure 45. supply current vs jmode fclk (mhz) supply current (a) 800 1200 1600 2000 2400 2800 3200 0 0.2 0.4 0.6 0.8 d124 bg calibration fg calibration lpbg calibration fclk (mhz) supply current (a) 800 1200 1600 2000 2400 2800 3200 0 0.2 0.4 0.6 0.8 d117 bg calibration fg calibration lpbg calibration decimation factor enob (bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8.5 9 9.5 10 10.5 d133 fin = 2400 mhz fin = 600 mhz jmode supply current (a) 0 2 4 6 8 10 12 14 16 18 0 0.25 0.5 0.75 1 1.25 1.5 d034 ia11 id11 ia19 fclk (mhz) power consumption (w) 800 1200 1600 2000 2400 2800 3200 2 2.5 3 3.5 4 d118 bg calibration fg calibration lpbg calibration decimation factor magnitude (dbfs) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 45 50 55 60 65 70 75 80 85 d035 snr (dbfs) sinad (dbfs) sfdr (dbfs)
34 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. f in = 2400 mhz f clk = 3200 mhz bg calibration figure 46. supply current vs jmode f in = 2400 mhz f clk = 3200 mhz figure 47. power consumption vs jmode jmode1 f clk = 3200 mhz fg calibration figure 48. dnl vs code jmode1 f clk = 3200 mhz fg calibration figure 49. inl vs code jmode1 f in = 350 mhz fg calibration figure 50. single tone fft at a in = -1dbfs jmode3 f in = 350 mhz fg calibration figure 51. single tone fft at a in = -1 dbfs frequency (hz) - fft plot magnitude (dbfs) 0 8e+8 1.6e+9 2.4e+9 3.2e+9 -150 -120 -90 -60 -30 0 snr = 56.9 dbfs sfdr = 65.0 dbfs enob = 8.80 bits d134 frequency (hz) - fft plot magnitude (dbfs) 0 4e+8 8e+8 1.2e+9 1.6e+9 -150 -120 -90 -60 -30 0 snr = 56.7 dbfs sfdr = 68.1 dbfs enob = 9.05 bits d139 jmode supply current (a) 0 2 4 6 8 10 12 14 16 18 0 0.25 0.5 0.75 1 1.25 1.5 d122 ia11 id11 ia19 jmode power consumption (w) 0 2 4 6 8 10 12 14 16 18 2.5 2.75 3 3.25 3.5 3.75 4 d033 bg calibration fg calibration code inl (lsb) 0 4095 -4 -2 0 2 4 d049 code dnl (lsb) 0 4095 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 d048
35 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode1 f in = 2700 mhz fg calibration figure 52. single tone fft at a in = -1 dbfs jmode3 f in = 2700 mhz fg calibration figure 53. single tone fft at a in = -1 dbfs jmode1 f in = 5000 mhz fg calibration figure 54. single tone fft at a in = -1 dbfs jmode3 f in = 5000 mhz fg calibration figure 55. single tone fft at a in = -1 dbfs jmode1 f in = 8200 mhz fg calibration figure 56. single tone fft at a in = -1 dbfs jmode3 f in = 8200 mhz fg calibration figure 57. single tone fft at a in = -1 dbfs frequency (hz) - fft plot magnitude (dbfs) 0 4e+8 8e+8 1.2e+9 1.6e+9 -150 -120 -90 -60 -30 0 snr = 55.0 dbfs sfdr = 59.1 dbfs enob = 8.57 bits d140 frequency (hz) - fft plot magnitude (dbfs) 0 4e+8 8e+8 1.2e+9 1.6e+9 -150 -120 -90 -60 -30 0 snr = 52.8 dbfs sfdr = 54.3 dbfs enob = 7.93 bits d141 frequency (hz) - fft plot magnitude (dbfs) 0 8e+8 1.6e+9 2.4e+9 3.2e+9 -150 -120 -90 -60 -30 0 snr = 55.5 dbfs sfdr = 56.0 dbfs enob = 8.55 bits d135 frequency (hz) - fft plot magnitude (dbfs) 0 8e+8 1.6e+9 2.4e+9 3.2e+9 -150 -120 -90 -60 -30 0 snr = 51.0 dbfs sfdr = 54.9 dbfs enob = 7.77 bits d144 frequency (hz) - fft plot magnitude (dbfs) 0 8e+8 1.6e+9 2.4e+9 3.2e+9 -150 -120 -90 -60 -30 0 snr = 53.5 dbfs sfdr = 53.5 dbfs enob = 7.89 bits d136 frequency (hz) - fft plot magnitude (dbfs) 0 4e+8 8e+8 1.2e+9 1.6e+9 -150 -120 -90 -60 -30 0 snr = 50.4 dbfs sfdr = 52.3 dbfs enob = 7.68 bits d145
36 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode1 f in = 8200 mhz fg calibration figure 58. single tone fft at a in = -16 dbfs jmode3 f in = 8200 mhz fg calibration figure 59. single tone fft at a in = -16 dbfs jmode2 f clk = 3200 mhz f in = 3199.9 mhz figure 60. background calibration core transition - ac signal jmode2 f clk = 3200 mhz f in = 3199.9 mhz figure 61. background calibration core transition - ac signal zoomed sample number sample value 0 5000 10000 15000 20000 25000 30000 35000 0 500 1000 1500 2000 2500 3000 3500 4000 zoomed area in following plot d125 sample number sample value 14400 14800 15200 15600 16000 16400 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 d126 frequency (hz) - fft plot magnitude (dbfs) 0 4e+8 8e+8 1.2e+9 1.6e+9 -150 -120 -90 -60 -30 0 snr = 57.1 dbfs sfdr = 73.9 dbfs enob = 9.13 bits d142 frequency (hz) - fft plot magnitude (dbfs) 0 8e+8 1.6e+9 2.4e+9 3.2e+9 -150 -120 -90 -60 -30 0 snr = 57.3 dbfs sfdr = 67.6 dbfs enob = 8.71 bits d137
37 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) typical values at t a = +25 c, va19 = 1.9v, va11 = vd11 = 1.1v, default full-scale voltage (fs_range_a = fs_range_b = 0xa000), input signal applied to ina+/- in single channel modes, f in = 347 mhz, a in = -1dbfs, f clk = maximum rated clock frequency, filtered, 1-vpp sine-wave clock, jmode=1, background calibration, unless otherwise noted. snr results exclude dc, hd2 to hd9 and interleaving spurs. sinad, enob and sfdr results exclude dc and fixed frequency interleaving spurs. jmode0 f clk = 3200 mhz dc input figure 62. background calibration core transition - dc signal jmode0 f clk = 3200 mhz dc input figure 63. background calibration core transition - dc signal zoomed sample number sample value 0 1000 2000 3000 4000 5000 6000 7000 8000 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 d127 +0.35v differential -0.35v differential 0v differential sample number sample value 1500 1650 1800 1950 2100 2250 2400 2550 0 50 100 150 200 250 300 350 400 450 500 d128 -0.35v differential
38 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview adc12dj3200 is an rf-sampling giga-sample adc that can directly sample input frequencies from dc to above 10 ghz. in dual channel mode, adc12dj3200 can sample up to 3200-msps and in single channel mode up to 6400-msps. programmable tradeoffs in channel count (dual channel mode) and nyquist bandwidth (single channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. full power input bandwidth (-3 db) of 8.0 ghz, with usable frequencies exceeding the -3 db point in both dual and single channel modes, allows direct rf sampling of l- band, s-band, c-band and x-band for frequency agile systems. time interleaving is achieved internally through 4 active cores. in dual channel mode, two cores are interleaved per channel to increase the sample rate to 2x the core sample rate. in single channel mode, all 4 cores are time interleaved to increase the sample rate to 4x the core sample rate. either input can be used in single channel mode, however performance has been optimized for ina+/ ? . the user provides a clock at 2x the adc core sample rate and the generation of the clocks for the interleaved cores is done internally for both single channel mode and dual channel mode. adc12dj3200 also provides foreground and background calibration options to match the gain and offset between cores to minimize spurious artifacts due to the interleaving. adc12dj3200 uses a high speed jesd204b output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. the serial output lanes support up to 12.8 gbps and can be configured to trade-off bit rate and number of lanes. innovative synchronization features, including noiseless aperture delay (t ad ) adjustment and sysref windowing, simplify system design for phased array radar and mimo communications. optional digital down converters (ddcs) in dual channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
39 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.2 functional block diagrams figure 64. adc12dj3200 functional block diagram 7.3 feature description 7.3.1 analog inputs the analog inputs of adc12dj3200 have internal buffers to enable high input bandwidth and isolate sampling capacitor glitch noise from the input circuit. analog inputs must be driven differentially since operation with a single-ended signal results in degraded performance. both ac coupling and dc coupling of the analog inputs is supported. the analog inputs are designed for an input common mode voltage (v cmi ) of 0 v which is terminated internally through single-ended 50- resistors to ground (gnd) on each input pin. dc-coupled input signals must have a common mode voltage that meets the device input common mode requirements specified as v cmi in recommended operating conditions . the 0-v input common mode voltage simplifies the interface to split-supply fully differential amplifiers and to a variety of transformers and baluns. adc12dj3200 includes internal analog input protection to protect the adc inputs during over-ranged input conditions (see analog input protection ). a simplified analog input model is shown in figure 65 . ddc bypass / single channel mode sclk sdi sdo scs\ ncoa0 ncoa1 ncob0 ncob1 adc a jesd204b link a jesd204b link b aperture delay adjust clock distribution and synchronization clk+ clk- sysref+ sysref- syncse\ over- range da0+ da0- da7+ da7- db0+ db0- db7+ db7- status indicators ora0 ora1 orb0 orb1 calstat adc b tdiode+ tdiode- caltrg pd spi registers and device control ina+ ina- inb+ inb- tmstp+ tmstp- input mux input mux ddc a mixer filter n nco bank a ddc bypass / single channel mode ddc b mixer filter n nco bank b jmode jmode sysref windowing digbind copyright ? 2016, texas instruments incorporated
40 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 65. adc12dj3200 analog input internal termination and protection there is minimal degradation in analog input bandwidth when using single channel mode versus dual channel mode. in single channel mode it is strongly recommended that ina+/ ? be used as the input to the adc since adc performance has been optimized for ina+/ ? . however, either analog input (ina+ and ina ? or inb+ and inb ? ) can be used. the use of inb+/ ? will result in degraded performance unless custom trim routines are used to optimize performance for inb+/ ? for each device. the desired input can be chosen using single_input in input mux control register (address = 0x060) [reset = 0x01] . note in single channel mode it is strongly recommended that ina+/ ? be used as the input to the adc for optimized performance. 7.3.1.1 analog input protection the analog inputs are protected against over-drive conditions by internal clamping diodes that are capable of sourcing or sinking input currents during over-range conditions, see voltage and current limits in absolute maximum ratings . the over-range protection is also defined for a peak rf input power in absolute maximum ratings , which is frequency independent. operation above the maximum conditions listed in recommended operating conditions will result in an increase in failure-in-time (fit) rate, so the system should correct the over- drive condition as quickly as possible. the analog input protection diodes are shown in figure 65 . 7.3.1.2 full-scale voltage (v fs ) adjustment input full-scale voltage (v fs ) adjustment is available, in fine increments, for each analog input through the fs_range_a ( ina full scale range adjust register (address = 0x030-0x031) [reset = 0xa000] ) register setting and fs_range_b ( inb full scale range adjust register (address = 0x032-0x033) [reset = 0xa000] ) register setting for ina+/ ? and inb+/ ? , respectively. the available adjustment range is specified in electrical characteristics - dc specifications . larger full-scale voltages improve snr and noise floor (in dbfs/hz) performance, but may degrade harmonic distortion. the full-scale voltage adjustment is useful for matching the full-scale range of multiple adcs when developing a multi-converter system or for external interleaving of multiple adc12dj3200 to achieve higher sampling rates. 7.3.1.3 analog input offset adjust the input offset voltage for each input can be adjusted through the oadj_x_iny registers (registers 0x08a and 0x095), where x represents the adc core (a, b, or c) and y represents the analog input (ina+/ ? or inb+/ ? ). the adjustment range is approximately 28 mv to ? 28 mv differential. see calibration modes and trimming for more information. adc 50 50 ina/b+ ina/b- agnd analog input protection diodes input buffer copyright ? 2016, texas instruments incorporated
41 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.2 adc core adc12dj3200 consists of a total of six adc cores. the cores are interleaved for higher sampling rates and swapped on-the-fly for calibration as required by the operating mode. this section highlights the theory and key features of the adc cores. 7.3.2.1 adc theory of operation the differential voltages at the analog inputs are captured by the rising edge of clk+/ ? in dual channel mode or by the rising and falling edges of clk+/ ? in single channel mode. after capturing the input signal, the adc converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. if the voltage on ina ? or inb ? is higher than the voltage on ina+ or inb+, respectively, then the digital output will be a negative 2's complement value. if the voltage on ina+ or inb+ is higher than the voltage on ina ? or inb ? , respectively, then the digital output will be a positive 2's complement value. the differential voltage at the input pins can be calculated from the digital output by equation 1 where code is the signed decimation output code (e.g. ? 2048 to +2047), n is the adc resolution and v fs is the full-scale input voltage of the adc as specified in recommended operating conditions , including any adjustment performed by programming fs_range_a or fs_range_b. (1) 7.3.2.2 adc core calibration adc core calibration is required to optimize analog performance of the adc cores. calibration must be repeated as operating conditions change significantly, namely temperature, in order to maintain optimal performance. the adc12dj3200 family has a built in calibration routine that can be run as a foreground operation or a background operation. foreground operation requires adc downtime, where the adc is no longer sampling the input signal, to complete the process. background calibration can be used to overcome this limitation and allow constant operation of the adc. see calibration modes and trimming for detailed information on each mode. 7.3.2.3 adc over-range detection to ensure that system gain management has the quickest-possible response time, a low-latency configurable over-range function is included. the over-range function works by monitoring the converted 12-bit samples at the adc to quickly detect if the adc is near saturation or already in an over-range condition. the absolute value of the upper 8 bits of the adc data are checked against two programmable thresholds, ovr_t0 and ovr_t1. these thresholds apply to both channel a and channel b in dual channel mode. the following table lists how an adc sample is converted to an absolute value for a comparison of the thresholds. table 1. conversion of adc sample for over-range comparison adc sample (offset binary) adc sample (2's complement) absolute value upper 8 bits used for comparison 1111 1111 1111 (4095) 0111 1111 1111 (+2047) 111 1111 1111 (2047) 1111 1111 (255) 1111 1111 0000 (4080) 0111 1111 0000 (+2032) 111 1111 0000 (2032) 1111 1110 (254) 1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0) 0000 0001 0000 (16) 1000 0001 0000 ( ? 2032) 111 1111 0000 (2032) 1111 1110 (254) 0000 0000 0000 (0) 1000 0000 0000 ( ? 2048) 111 1111 1111 (2047) 1111 1111 (255) if the upper 8 bits of the absolute value equal or exceed the ovr_t0 or ovr_t1 thresholds during the monitoring period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. in dual channel mode the over-range status can be monitored on the ora0 and ora1 pins for channel a and orb0 and orb1 pins for channel b, where orx0 corresponds to the ovr_t0 threshold and orx1 corresponds to the ovr_t1 threshold. in single channel mode the over-range status for threshold ovr_t0 is determined by monitoring both ora0 and orb0 outputs while the ovr_t1 threshold is determined by monitoring both ora1 and orb1 outputs. in single channel mode the two outputs for each threshold should be or'd together to determine whether an over-range condition occurred. ovr_n can be used to set the output pulse duration from the last over-range event. table 2 lists the over-range pulse lengths for the various ovr_n settings ( over-range configuration register (address = 0x213) [reset = 0x07] ). in decimation modes (only in the fs n in v code v 2
42 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated jmodes where cs = 1 in table 18 ), the over-range status is also embedded into the output data samples. for complex decimation modes the ovr_t0 threshold status is embedded as the lsb along with the upper 15 bits of every complex i sample and ovr_t1 threshold status is embedded as the lsb along with the upper 15 bits of every complex q sample. for real decimation modes the ovr_t0 threshold status is embedded as the lsb of every even numbered sample and ovr_t1 threshold status is embedded as the lsb of every odd numbered sample. table 3 lists the outputs, related data samples, threshold settings and the monitoring period equation. the embedded over-range bit will go high if the associated channel has exceeded the associated over-range threshold within the monitoring period set by ovr_n. the monitoring period can be calculated as shown in table 3 .. table 2. over-range monitoring period for ora0, ora1, orb0 and orb1 outputs ovr_n over-range pulse length since last over-range event (devclk cycles) 0 8 1 16 2 32 3 64 4 128 5 256 6 512 7 1024 (1) ovr_n is the monitoring period register setting. table 3. threshold and monitoring period for embedded over-range indicators in dual channel decimation modes over-range indicator associated threshold decimation type over-range status embedded in monitoring period (adc samples) ora0 ovr_t0 real decimation (jmode 9) channel a even numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel a in-phase (i) samples 2 ovr_n (1) ora1 ovr_t1 real decimation (jmode 9) channel a odd numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel a quadrature (q) samples 2 ovr_n (1) orb0 ovr_t0 real decimation (jmode 9) channel b even numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel b in-phase (i) samples 2 ovr_n (1) orb1 ovr_t1 real decimation (jmode 9) channel b odd numbered samples 2 ovr_n+1 (1) complex down-conversion (jmode 10-16, except jmode 12) channel b quadrature (q) samples 2 ovr_n (1) typically, the ovr_t0 threshold can be set near the full-scale value (228 for example). when the threshold is triggered, a typical system can turn down the system gain to avoid clipping. the ovr_t1 threshold can be set much lower. for example, the ovr_t1 threshold can be set to 64 (peak input voltage of ? 12 dbfs). if the input signal is strong, the ovr_t1 threshold is tripped occasionally. if the input is quite weak, the threshold is never tripped. the downstream logic device monitors the ovr_t1 bit. if ovr_t1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above ? 12 dbfs).
43 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.2.4 code error rate (cer) adc cores can generate bit errors within a sample, often called code errors (cer) or referred to as sparkle codes, due to metastability caused by non-ideal comparator limitations. the adc12dj3200 uses a unique adc architecture that inherently allows significant code error rate improvements from traditional pipelined flash or successive approximation register (sar) adcs. the code error rate of the adc12dj3200 is multiple orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing significant signal reliability improvements. 7.3.3 timestamp tmstp+ and tmstp ? differential input can be used as a time-stamp input to mark a specific sample based on the timing of an external trigger event relative to the sampled signal. timestamp_en ( lsb control bit output register (address = 0x160) [reset = 0x00] ) must be set in order to use the timestamp feature and output the timestamp data. when enabled, the lsb of the 12-bit adc digital output reports the status of the tmstp+/ ? input. in effect, the 12-bit output sample consists of the upper 11-bits of the 12-bit converter and the lsb of the 12-bit output sample is the output of a parallel 1-bit converter (tmstp+/ ? )with the same latency as the adc core. in the 8-bit operating modes, the lsb of the 8-bit output sample is used to output the timestamp status. the trigger must be applied to the differential tmstp+ and tmstp ? inputs. the trigger can be asynchronous to the adc sampling clock and is sampled at approximately the same time as the analog input. timestamp cannot be used when a jmode with decimation is selected and instead sysref should be used to achieve synchronization through jesd204b's subclass-1 method for achieving deterministic latency. 7.3.4 clocking the clocking subsystem of adc12dj3200 has two input signals, device clock (clk+, clk ? ) and sysref (sysref+, sysref ? ). within the clocking subsystem there is a noiseless aperture delay adjustment (t ad adjust), a clock duty cycle corrector and a sysref capture block. the clocking subsystem is shown in figure 66 . figure 66. adc12dj3200 clocking subsystem sysref capture t ad adjust clock distribution and synchronization (adc cores, digital, jesd204b, etc.) clk+ clk- sysref+ sysref- sysref windowing automatic sysref calibration sysref_pos sysref_sel tad_ inv tad_ coarse tad_fine src_en duty cycle correction copyright ? 2016, texas instruments incorporated
44 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated the device clock is used as the sampling clock for the adc core as well as the clocking for the digital processing and serializer outputs. a low noise (low jitter) device clock should be used to maintain high signal-to-noise ratio (snr) within the adc. in dual channel mode the analog input signal for each input is sampled on the rising edge of the device clock. in single channel mode both the rising and falling edge of the device clock are used to capture the analog signal to reduce the max clock rate required by the adc. a noiseless aperture delay adjustment (t ad adjust) allows the user to shift the sampling instance of the adc in fine steps in order to synchronize multiple adc12dj3200 or to fine tune system latency. duty cycle correction is implemented in adc12dj3200 to ease the requirements on the external device clock while maintaining high performance. table 4 summarizes the device clock interface in dual channel mode and single channel mode. table 4. device clock vs. mode of operation mode of operation sampling rate vs. f clk sampling instant dual channel mode 1 x f clk rising edge single channel mode 2 x f clk rising and falling edge sysref is a system timing reference used for jesd204b subclass-1 implementations of deterministic latency. sysref is used to achieve deterministic latency and for multi-device synchronization. sysref must be captured by the correct device clock edge in order to achieve repeatable latency and synchronization. adc12dj3200 includes sysref windowing and automatic sysref calibration to ease the requirements on the external clocking circuits and simplify the synchronization process. sysref can be implemented as a single pulse or as a periodic clock. in periodic implementations, sysref must be equal to, or an integer division of, the local multi-frame clock frequency. valid sysref frequencies can be calculated using equation 2 where r and f are set by the jmode setting (see table 18 ), f clk is the device clock frequency (clk+/ ? ), k is the programmed multi-frame length (see table 18 for valid k settings) and n is any positive integer. (2) 7.3.4.1 noiseless aperture delay adjustment (t ad adjust) adc12dj3200 contains a delay adjustment on the device clock (sampling clock) input path, called t ad adjust, that can be used to shift the sampling instance within the device in order to align sampling instances among multiple devices or for external interleaving of multiple adc12dj3200. further, t ad adjust can be used for automatic sysref calibration to simplify synchronization ( automatic sysref calibration ). aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation in aperture jitter (t aj ) is possible at large values of tad_coarse due to internal clock path attenuation. the degradation in aperture jitter may result in minor snr degradations at high input frequencies (see t aj in switching characteristics ). the feature is programmed using tad_inv, tad_coarse and tad_fine in devclk aperture delay adjustment register (address = 0x2b5 to 0x2b7) [reset = 0x000000] . setting tad_inv inverts the input clock resulting in a delay equal to half the clock period. tad_coarse and tad_fine are variable analog delays with step sizes and ranges summarized in table 5 . all three delay options are independent and can be used in conjunction. all clocks within the device are shifted by the programmed t ad adjust amount, which results in a shift of the timing of the jesd204b serialized outputs and affects the capture of sysref. table 5. t ad adjust adjustment ranges adjustment parameter adjustment step delay settings maximum delay tad_inv 1/(f clk * 2) 1 1/(f clk * 2) tad_coarse see t tad(step) in switching characteristics 256 see t tad(max) in switching characteristics tad_fine see t tad(step) in switching characteristics 256 see t tad(max) in switching characteristics please note that to maintain timing alignment between converters it is also important to provide stable and matched power supply voltages and device temperatures. aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to the jesd204b data link. it is recommended to use tad_ramp to reduce the probability of the jesd204b link losing synchronization. see aperture delay ramp control (tad_ramp) . n k f f r f clk sysref u u u u 10
45 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.4.2 aperture delay ramp control (tad_ramp) adc12dj3200 contains a function to gradually adjust the t ad adjust setting towards the newly written tad_coarse value. this will allow the t ad adjust setting to be adjusted with minimal glitching of the internal clock circuitry. the tad_ramp_rate parameter allows either a slower (1 tad_coarse lsb per 256 t clk cycles) or faster ramp (4 tad_coarse lsbs per 256 t clk cycles) to be selected. the tad_ramp_en parameter enables the ramp feature and any subsequent writes to tad_coarse initiate a new cramp. 7.3.4.3 sysref capture for multi-device synchronization and deterministic latency the clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. adc12dj3200 uses the subclass-1 method of jesd204b to achieve deterministic latency and synchronization. subclass 1 requires that the sysref signal be captured by a deterministic device clock (clk+/-) edge at each system power on and at each device in the system. this requirement imposes setup and hold constraints on sysref relative to clk+/- which can be difficult to meet at giga-sample clock rates over all system operating conditions. adc12dj3200 includes a number of features to simplify this synchronization process and relax system timing constraints. ? adc12dj3200 uses dual-edge sampling (des) in single-channel mode to reduce the clk+/- input frequency by half and double the timing window for sysref (see table 4 ) ? a sysref position detector (relative to clk+/-) and selectable sysref sampling position aid the user in meeting setup and hold times over all conditions (see sysref position detector and sampling position selection (sysref windowing) ) ? easy-to-use automatic sysref calibration uses the aperture timing adjust block (t ad adjust) to shift the adc sampling instance based on the phase of sysref (rather than adjusting sysref based on the phase of the adc sampling instance) (see automatic sysref calibration ) 7.3.4.3.1 sysref position detector and sampling position selection (sysref windowing) the sysref windowing block is used to first detect the position of sysref relative to the clk+/- rising edge and then to select a desired sysref sampling instance, which is a delay version of clk+/-, to maximize setup and hold timing margins. in many cases a single sysref sampling position (sysref_sel) is sufficient to meet timing for all systems (part-to-part variation) and conditions (temperature and voltage variations). however, the feature can also be used by the system to expand the timing window by tracking the movement of sysref as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system. use of the sysref windowing block is as follows. first, the device clock and sysref should be applied to the device. the location of sysref relative to the device clock cycle is determined and stored in sysref_pos in figure 98 . each bit of sysref_pos represents a potential sysref sampling position. if a bit in sysref_pos is set to '1', then the corresponding sysref sampling position has a potential setup or hold violation. upon determining the valid sysref sampling positions (the positions of sysref_pos that are set to '0') the desired sampling position can be chosen by setting sysref_sel in clock control register 0 (address = 0x029) [reset = 0x00] to the value corresponding to that sysref_pos position. in general the middle sampling position between two setup and hold instances should be chosen. ideally, sysref_pos and sysref_sel should be performed at the system's nominal operating conditions (temperature and supply voltage) to provide maximum margin for operating condition variations. this process can be performed at final test and the optimal sysref_sel setting can be stored for use at every system power up. further, sysref_pos can be used to characterize the skew between clk+/ ? and sysref+/ ? over operating conditions for a system by sweeping the system temperature and supply voltages. for systems that have large variations in clk+/ ? to sysref+/ ? skew this characterization can be used to track the optimal sysref sampling position as system operating conditions change. in general, a single value can be found that meets timing over all conditions for well matched systems, such as those where clk+/ ? and sysref+/ ? come from a single clocking device. note sysref_sel should be set to '0' when using automatic sysref calibration ( automatic sysref calibration ).
46 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated the step size between each sysref_pos sampling position can be adjusted using sysref_zoom. when sysref_zoom is set to '0', the delay steps are more coarse. when sysref_zoom is set to '1', the delay steps finer steps. see switching characteristics for delay step sizes when sysref_zoom is enabled and disabled. in general, sysref_zoom should always be used (sysref_zoom = 1) unless a transition region (defined by 1's in sysref_pos) is not seen, such as could be the case for low clock rates. bits 0 and 23 of sysref_pos will always be set to '1' since it cannot be determined if these settings are close to a timing violation, although the actual valid window could extend beyond these sampling positions. the value programmed into sysref_sel is the decimal number representing the desired bit location in sysref_pos. table 6 shows some example sysref_pos readings and the optimal sysref_sel settings. although 24 sampling positions are provided by the sysref_pos status register, sysref_sel only allows selection of the first 16 sampling positions, corresponding to sysref_pos bits 0 to 15. the additional sysref_pos status bits are intended only to provide additional knowledge of the sysref valid window. in general, lower values of sysref_sel should be selected due to variation of the delays over supply voltage, however in the fourth example a value of 15 provides additional margin and may be selected instead. table 6. examples of sysref_pos readings and sysref_sel selections sysref_pos[23:0] optimal sysref_sel setting 0x02e[7:0] (largest delay) 0x02d[7:0] 0x02c[7:0] (smallest delay) b10000000 b011000 00 b00011001 8 or 9 b10011000 b000 0 0000 b00110001 12 b10000000 b01100000 b 00 000001 6 or 7 b10000000 b 0 0000011 b000 0 0001 4 or 15 b10001100 b01100011 b0 0 011001 6 7.3.4.3.2 automatic sysref calibration adc12dj3200 has an automatic sysref calibration feature to alleviate the often challenging setup and hold times associated with capturing sysref for giga-sample data converters. automatic sysref calibration uses the t ad adjust feature to shift the device clock to maximize the sysref setup and hold times or align the sampling instance based on the sysref rising edge. adc12dj3200 must have a proper device clock applied and be programmed for normal operation before starting automatic sysref calibration. when ready to initiate automatic sysref calibration a continuous sysref signal should be applied. note that sysref must be a continuous (periodic) signal when using automatic sysref calibration. start the calibration process by setting src_en high in figure 173 after configuring automatic sysref calibration using the src_cfg register. upon setting src_en high adc12dj3200 searches for the optimal t ad adjust setting until the device clock falling edge is internally aligned to the sysref rising edge. tad_done in figure 175 can be monitored to ensure that sysref calibration has finished. by aligning the device clock falling edge with the sysref rising edge automatic sysref calibration maximizes the internal sysref setup and hold times relative to the device clock while also setting the sampling instant based on the sysref rising edge. after automatic sysref calibration finishes the rest of the startup procedure can be performed to finish bringing up the system. for multi-device synchronization the timing of the sysref rising edge should be matched at all devices and therefore trace lengths should be matched from a common sysref source to each adc12dj3200. any skew between the sysref rising edge at each device will result in additional error in the sampling instance between devices, however repeatable deterministic latency from system startup to startup through each device should still be achieved. no other design requirements are needed in order to achieve multi-device synchronization as long as a proper elastic buffer release point is chosen in the receiver. a timing diagram of the sysref calibration procedure is shown in figure 67 . the optimized setup and hold times are shown as t su(opt) and t h(opt) , respectively. device clock and sysref are referred to as "internal" in this diagram since the phase of the internal signals are aligned within the device and not to the external (applied) phase of device clock or sysref.
47 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 67. sysref calibration timing diagram once finished, the t ad adjust setting found by automatic sysref calibration can be read from src_tad in figure 175 . after calibration, the system will continue to use the calibrated t ad adjust setting for operation until the system is powered down. however, if desired, the user can then disable sysref calibration and fine-tune the t ad adjust setting according to the systems needs. alternatively, the use of automatic sysref calibration can be done at product test (or periodic re-calibration) of the optimal t ad adjust setting for each system. this value can be stored and written to the tad register (tad_inv, tad_coarse and tad_fine) upon system startup. sysref calibration should not be run while adc calibration (foreground or background) is running. if background calibration is the desired use case, it should be disabled while sysref calibration is used, then reenabled after tad_done goes high. sysref_sel in clock control register 0 (address = 0x029) [reset = 0x00] must be set to 0 when using sysref calibration. sysref calibration will search the tad_coarse delays using both non-inverted (tad_inv = 0) and inverted clock polarity (tad_inv = 1) to minimize the required tad_coarse setting in order to minimize loss on the clock path to reduce aperture jitter (t aj ). 7.3.5 digital down converters (dual channel mode only) after converting the analog voltage to a digital value, the digitized sample can either be sent directly to the jesd204b interface block (ddc bypass) or it can be sent to the digital down conversion (ddc) block for frequency conversion and decimation (in dual channel mode only). frequency conversion and decimation allow a specific frequency band to be selected and output in the digital data stream while reducing the effective data rate and interface speed or width. the ddc is designed such that the digital processing does not degrade the noise spectral density (nsd) performance of the adc. the digital down converter for channel a of the adc12dj3200 is shown in figure 68 . channel b has the same structure with the input data selected by dig_bind_b and the nco selection mux controlled by pins ncob[1:0] or through cselb[1:0]. sampled input signal internal unadjusted device clock internal sysref src_en (spi register bit) t h(opt) t su(opt) internal calibrated device clock before calibration, device clock falling edge does not align with sysref rising edge t tad(src) calibration enabled after calibration, device clock falling edge aligns with sysref rising edge t cal(src) tad_done (spi register bit) calibration finished
48 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 68. channel a digital down conversion block (dual channel mode only) 7.3.5.1 numerically controlled oscillator and complex mixer the ddc contains a complex numerically-controlled oscillator (nco) and a complex mixer. the oscillator generates a complex exponential sequence as shown in equation 3 . x[n] = e j n (3) the frequency ( ) is specified by a 32-bit register setting. the complex exponential sequence is multiplied by the real input from the adc to mix the desired carrier to a frequency equal to f in +f nco , where f in is the analog input frequency after aliasing (in undersampling systems) and f nco is the programmed nco frequency. 7.3.5.1.1 nco fast frequency hopping (ffh) fast frequency hopping (ffh) is made possible by each ddc having four independent ncos that can be controlled by the ncoa0 and ncoa1 pins for ddc a and ncob0 and ncob1 pins for ddc b. each nco has independent frequency settings ( basic nco frequency setting mode ) and initial phase settings ( nco phase offset setting ) that can be set independently. further, all ncos have independent phase accumulators that continue to run when the specific nco is not selected, allowing the ncos to maintain their phase between selection so that downstream processing does not need to perform carrier recovery after each hop, for instance. nco bank a complex mixer n mux ncoa[1:0] or csela[1:0] 2 decimate-by-n (based on jmode) spectral inversion 2 mux high pass low pass mux mux real 12-bit @ fs complex 15-bit @ fs/n 2 real 15-bit @ fs/2 mux dig_bind_a d2_high_pass invert_spectrum mux jmode (ddc bypass) jmode adc channel a adc channel b jesd204b copyright ? 2016, texas instruments incorporated
49 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 69. nco fast frequency hopping latency diagram nco hopping occurs when the nco gpio pins change state. the pins are controlled asynchronously and therefore synchronous switching is not possible. associated latencies are demonstrated in figure 69 , where t tx and t adc are provided in switching characteristics . all latencies in table 7 are approximations only. table 7. nco fast frequency hopping latency definitions latency parameter value or calculation units t gpio-mixer ~36 to ~40 t clk cycles t adc-mixer ~36 t clk cycles t mixer-tx (t tx + t adc ) ? t adc-mixer t clk cycles 7.3.5.1.2 nco selection within each channel's ddc, four different frequency and phase settings are available for use. each of the four settings uses a different phase accumulator within the nco. since all four phase accumulators are independent and continuously running, rapid switching between different nco frequencies is possible allowing for phase coherent frequency hopping. the specific frequency-phase pair used for each channel is selected through the ncoa[1:0] or ncob[1:0] input pins when cmode is set to 1. alternatively, the selected nco can be chosen through spi by csela for ddc a and cselb for ddc b by setting cmode to 0 (default). the logic table for nco selection is provided in table 8 for both gpio and spi selection options. table 8. logic table for nco selection using gpio or spi nco selection cmode ncox1 ncox0 cselx[1] cselx[0] nco 0 using gpio 1 0 0 x x nco 1 using gpio 1 0 1 x x nco 2 using gpio 1 1 0 x x nco 3 using gpio 1 1 1 x x nco 0 using spi 0 x x 0 0 nco 1 using spi 0 x x 0 1 nco 2 using spi 0 x x 1 0 nco 3 using spi 0 x x 1 1 ddc block nco bank a complex mixer n mux ncox[1:0] decimate-by-n (based on jmode) adc jesd204b t gpio-mixer t mixer-tx dx0+/- dx1+/- dx2+/- dx7+/- inx+ inx- t adc-mixer copyright ? 2016, texas instruments incorporated
50 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated the frequency for each phase accumulator is programmed independently through the freqax, freqbx (x=0 to 3) and, optionally, nco_rdiv register settings. the phase offset for each accumulator is programmed independently through the phaseax and phasebx (x=0 to 3) register settings. 7.3.5.1.3 basic nco frequency setting mode in basic nco frequency-setting mode (nco_rdiv = 0x0000), the nco frequency setting is set by the 32-bit register value, freqax and freqbx (x = 0 to 3). the nco frequency for ddc a can be calculated using equation 4 , where freqax can be replaced by freqbx to calculate the nco frequency for ddc b. ? (nco) = freqax 2 ? 32 ? (devclk) (x = 0 ? 3) (4) note changing the freqax and freqbx register settings results in non-deterministic nco phase. if deterministic phase is required the ncos must be resynchronized. see nco phase synchronization . 7.3.5.1.4 rational nco frequency setting mode in basic nco frequency mode, the frequency step size is very small and many frequencies can be synthesized, but sometimes an application requires very specific frequencies that fall between two frequency steps. for example with ? s equal to 2457.6 mhz and a desired ? (nco) equal to 5.02 mhz the value for freqax is 8773085.867. truncating the fractional portion results in an ? (nco) equal to 5.0199995 mhz, which is not the desired frequency. to produce the desired frequency, the nco_rdiv parameter is used to force the phase accumulator to arrive at specific frequencies without error. first, select a frequency step size ( ? (step) ) that is appropriate for the nco frequency steps required. the typical value of ? (step) is 10 khz. next, program the nco_rdiv value according to equation 5 . (5) the result of equation 5 must be an integer value. if the value is not an integer, adjust either of the parameters until the result is an integer value. for example, select a value of 1920 for nco_rdiv. note nco_rdiv values larger than 8192 can degrade the nco sfdr performance and are not recommended. now use equation 6 to calculate the freqax register value. (6) alternatively, the following equations can be used: (7) (8) table 9. common nco_rdiv values (for 10-khz frequency steps) ? (devclk) (mhz) nco_rdiv 3200 5000 3072 4800 2949.12 4608 2457.6 3840 ( ) 26 freqax round 2 n / nco_rdiv = ( ) 32 nco devclk freqax / round 2 = | | (nco) (step) | n | ( ) devclk step / nco _ rdiv 64 | | =
51 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 9. common nco_rdiv values (for 10-khz frequency steps) (continued) ? (devclk) (mhz) nco_rdiv 1966.08 3072 1600 2500 1474.56 2304 1228.8 1920 7.3.5.1.5 nco phase offset setting the nco phase-offset setting for each nco is set by the 16-bit register value phaseax and phasebx (where x = 0 to 3). the value is left-justified into a 32-bit field and then added to the phase accumulator. use equation 9 to calculate the phase offset in radians. (rad) = phasea/bx 2 ? 16 2 (x=0 to 3) (9) 7.3.5.1.6 nco phase synchronization the ncos must be synchronized after setting or changing the value of freqax or freqbx. nco synchronization is performed when the jesd204b link is initialized or by sysref, based on the settings of nco_sync_ila and nco_sync_next. the procedures are given below for the jesd204b initialization procedure and the sysref procedure for both dc coupled and ac coupled sysref signals. nco synchronization using jesd204b sync signal ( syncse or tmstp+/ ? ): 1. device must be programmed for normal operation 2. set nco_sync_ila to 1 3. set jesd_en to 0 4. program freqax, freqbx, phaseax and phasebx to the desired settings 5. in jesd204b receiver (logic device) deassert sync signal by setting it high 6. set jesd_en to 1 7. assert sync signal by setting it low in jesd204b receiver to start cgs process 8. after achieving cgs, deassert sync signal by setting it high at the same time for all adcs that are to be synchronized and verify that sync setup and hold times are met (specified in timing requirements ) nco synchronization using sysref (dc coupled): 1. device must be programmed for normal operation 2. set jesd_en to 1 to start jesd204b link (sync signal can respond as normal during cgs process) 3. program freqax, freqbx, phaseax and phasebx to the desired settings 4. verify that sysref is disabled (held low) 5. arm nco synchronization by setting nco_sync_next to 1 6. issue a single sysref pulse to all adcs to synchronize ncos within all devices nco synchronization using sysref (ac coupled): 1. device must be programmed for normal operation 2. set jesd_en to 1 to start jesd204b link (sync signal can respond as normal during cgs process) 3. program freqax, freqbx, phaseax and phasebx to the desired settings 4. run sysref continuously 5. arm nco synchronization by setting nco_sync_next to 1 at the same time at all adcs by timing the rising edge of sclk for the last data bit (lsb) at the end of the spi write so that it occurs after a sysref rising edge and early enough before the next sysref rising edge so that the trigger is armed before the next sysref rising edge (long sysref period is recommended) 6. ncos in all adcs will be synchronized by the next sysref rising edge
52 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.5.2 decimation filters the decimation filters are arranged to provide a programmable overall decimation of 2, 4, 8 or 16. all filter outputs have a resolution of 15 bits. the decimate-by-2 filter has a real output, while the decimate-by-4, decimate-by-8, and decimate-by-16 filters have complex outputs. table 10 lists the effective output sample rates, available signal bandwidths, output formats and stop-band attenuation for each decimation mode. note that the available bandwidths of the complex output modes are higher than expected for the given decimation factor or output sample rate due to the pair i/q nature of the output data. this results in the decimate-by-2 real and decimate-by-4 complex modes having approximately the same useful output bandwidth. table 10. output sample rates and signal bandwidths decimation setting ? (devclk) output format output rate (msps) max alias protected signal bandwidth (mhz) stop-band attenuation pass-band ripple no decimation ? (devclk) ? (devclk) / 2 n/a < +/ ? 0.001 db real signal, 12-bit data decimate-by-2 ? (devclk) / 2 0.4 x ? (devclk) / 2 > 89 db < +/ ? 0.001 db real signal, 15-bit data decimate-by-4 (d4_ap87 = 0) ? (devclk) / 4 0.8 x ? (devclk) / 4 > 90 db < +/ ? 0.001 db complex signal, 15- bit data decimate-by-4 (d4_ap87 = 1) ? (devclk) / 4 0.875 x ? (devclk) / 4 > 66 db < +/ ? 0.005 db complex signal, 15- bit data decimate-by-8 ? (devclk) / 8 0.8 x ? (devclk) / 8 > 90 db < +/ ? 0.001 db complex signal, 15- bit data decimate-by-16 ? (devclk) / 16 0.8 x ? (devclk) / 16 > 90 db < +/ ? 0.001 db complex signal, 15- bit data the composite decimation filter responses are given in the figures below. the passband section (black trace) shows the alias protected region of the response. the transition band (red trace) shows the transition region of the response, or the regions that alias into the transition region, which is not alias protected and therefore no desired signals should be within this band. the aliasing band (blue trace) shows the attenuation applied to the bands that alias back into the passband after decimation and are sufficiently low to prevent undesired signals from showing up in the passband. analog input filtering should be used for addition attenuation of the aliasing band or to prevent harmonics, interleaving spurs or other undesired spurious signals from folding into the desired signal band before the decimation filter. figure 70. decimate-by-2 composite response (d2_high_pass = 0) figure 71. decimate-by-2 composite zoomed passband response (d2_high_pass = 0) normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.05 0.1 0.15 0.2 0.25 -0.001 -0.0005 0 0.0005 0.001 h2co passband transition band
53 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 72. decimate-by-2 composite response (d2_high_pass = 1) figure 73. decimate-by-2 composite zoomed passband response (d2_high_pass = 1) figure 74. decimate-by-4 composite response (d4_ap87 = 0) figure 75. decimate-by-4 composite zoomed passband response (d4_ap87 = 0) figure 76. decimate-by-4 composite response (d4_ap87 = 1) figure 77. decimate-by-4 composite zoomed passband response (d4_ap87 = 1) normalized frequency (fs) attenuation (db) 0.25 0.3 0.35 0.4 0.45 0.5 -0.001 -0.0005 0 0.0005 0.001 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h2co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 -0.001 -0.0005 0 0.0005 0.001 h4co passband transition band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h4co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h4_9 passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 -0.01 -0.005 0 0.005 0.01 h4_9 passband transition band
54 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 78. decimate-by-8 composite response figure 79. decimate-by-8 composite zoomed passband response figure 80. decimate-by-16 composite response figure 81. decimate-by-16 composite zoomed passband response for maximum efficiency a group of high speed filter blocks are implemented with specific blocks used for each decimation setting to achieve the composite responses shown in the previous figures. table 11 describes the combination of filter blocks used for each decimation setting and table 12 lists the coefficient details and decimation factor of each filter block. the coefficients are symmetric with the center tap indicated by bold text. table 11. decimation mode filter usage decimation setting filter blocks used 2 cs80 4 (d4_ap87 = 0) cs45, cs80 4 (d4_ap87 = 1) cs45, cs87 8 cs20, cs40, cs80 16 cs10, cs20, cs40, cs80 normalized frequency (fs) attenuation (db) 0 0.01 0.02 0.03 0.04 0.05 0.06 -0.001 -0.0005 0 0.0005 0.001 h8co passband transition band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h8co passband transition band aliasing band normalized frequency (fs) attenuation (db) 0 0.005 0.01 0.015 0.02 0.025 0.03 -0.001 -0.0005 0 0.0005 0.001 h16c passband transition band normalized frequency (fs) attenuation (db) 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 h16c passband transition band aliasing band
55 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 12. filter coefficient details filter coefficient set (decimation factor of filter) cs10 (2) cs20 (2) cs40 (2) cs45 (2) cs80 (2) cs87 (2) ? 65 ? 65 109 109 ? 327 ? 327 56 56 ? 37 ? 37 ? 15 ? 15 0 0 0 0 0 0 0 0 0 0 0 0 577 577 ? 837 ? 837 2231 2231 ? 401 ? 401 118 118 23 23 1024 0 0 0 0 0 0 0 0 0 0 4824 4824 ? 8881 ? 8881 1596 1596 ? 291 ? 291 ? 40 ? 40 8192 0 0 0 0 0 0 0 0 39742 39742 ? 4979 ? 4979 612 612 64 64 65536 0 0 0 0 0 0 20113 20113 ? 1159 ? 1159 ? 97 ? 97 32768 0 0 0 0 2031 2031 142 142 0 0 0 0 ? 3356 ? 3356 ? 201 ? 201 0 0 0 0 5308 5308 279 279 0 0 0 0 ? 8140 ? 8140 ? 380 ? 380 0 0 0 0 12284 12284 513 513 0 0 0 0 ? 18628 ? 18628 ? 690 ? 690 0 0 0 0 29455 29455 939 939 0 0 0 0 ? 53191 ? 53191 ? 1313 ? 1313 0 0 0 0 166059 166059 1956 1956 262144 0 0 ? 3398 ? 3398 0 0 10404 10404 16384 7.3.5.3 output data format the ddc output data varies depending on the selected jmode. real decimate-by-2 mode (jmode 9) consists of 15-bit real output data. complex decimation modes (jmode 10 to 16), except for jmode 12, consist of 15 ? bit complex data plus the two over-range threshold-detection control bits. jmode 12 output data consists of 12-bit complex data, but does not include the two over-range threshold-detection control bits which should instead be monitored using the ora0/1 and orb0/1 output pins. the following table lists the data format: table 13. real decimation (jmode 9) output sample format ddc channel odd/ even sample 16-bit output word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a even ddc a even numbered sample 15-bit output data ovr_t0 a odd ddc a odd numbered sample 15-bit output data ovr_t1 b even ddc b even numbered sample 15-bit output data ovr_t0 b odd ddc b odd numbered sample 15-bit output data ovr_t1
56 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 14. complex decimation output sample format (except jmode 12) i/q sample 16-bit output word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i ddc in-phase (i) 15-bit output data ovr_t0 q ddc quadrature (q) 15-bit output data ovr_t1 7.3.5.4 decimation settings 7.3.5.4.1 decimation factor the decimation setting is adjustable over the following settings and is set by the jmode parameter. see table 18 for the available jmode values and the corresponding decimation settings. ? ddc bypass: no decimation, real output ? decimate-by-2: real output (jmode 9) ? decimate-by-4: complex output (jmode 10 to 12) ? decimate-by-8: complex output (jmode 13 to 14) ? decimate-by-16: complex output (jmode 15 to 16) 7.3.5.4.2 ddc gain boost the ddc gain boost ( ddc configuration register (address = 0x210) [reset = 0x00] ) provides additional gain through the ddc block. setting boost to 1 sets the total decimation filter chain gain to 6.02-db. with a setting of 0, the total decimation filter chain has a 0-db gain. this setting should only be used when the negative image of the input signal is filtered out by the decimation filters, otherwise clipping may occur. there is no reduction in analog performance when gain boost is enabled or disabled, but care should be taken to understand the reference output power for proper performance calculations. 7.3.6 jesd204b interface adc12dj3200 uses the jesd204b high-speed serial interface for data converters to transfer data from the adc to the receiving logic device. adc12dj3200 serialized lanes are capable of operating up to 12.8 gbps, slightly above the jesd204b max lane rate. a maximum of sixteen lanes can be used to allow lower lane rates for interfacing with speed limited logic devices. figure 82 shows a simplified block diagram of the jesd204b interface protocol. figure 82. simplified jesd204b interface diagram the various signals used in the jesd204b interface and the associated adc12dj3200 pin names are summarized briefly in table 15 for reference. adc jesd204b transport layer scrambler (optional) jesd204b link layer jesd204b tx 8b/10b encoder application layer jesd204b transport layer descramble (optional) jesd204b link layer jesd204b rx 8b/10b decoder adc jesd204b block logic device jesd204b block analog channel copyright ? 2016, texas instruments incorporated
57 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 15. summary of jesd204b signals signal name adc12dj3200 pin names description data da0+...da7+, da0 ? ...da7 ? , db0+...db7+, db0 ? ...db7 ? high-speed serialized data after 8b/10b encoding sync syncse, tmstp+, tmstp ? link initialization signal (handshake), toggles low to start code group synchronization (cgs) process device clock clk+, clk ? adc sampling clock, also used for clocking digital logic and output serializers sysref sysref+, sysref ? system timing reference used to deterministically reset the internal local multiframe counters in each jesd204b device 7.3.6.1 transport layer the transport layer takes samples from the adc output (in decimation bypass mode) or from the ddc output and maps the samples into octets, frames, multiframes and lanes. sample mapping is defined by the jesd204b mode that is used, defined by parameters such as l, m, f, s, n, n', cf, etc. there are a number of predefined transport layer modes in the adc12dj3200 which are defined in table 18 . the high level configuration parameters for the transport layer in adc12dj3200 are described in table 16 . for simplicity, the transport layer mode is chosen by simply setting the jmode parameter and the desired k value. for reference, the various configuration parameters for jesd204b are defined in table 17 . 7.3.6.2 scrambler an optional data scrambler can be used to scramble the octets before transmission across the channel. scrambling is recommended in order to remove the possibility of spectral peaks in the transmitted data. the jesd204b receiver automatically synchronizes its descrambler to the incoming scrambled data stream. the initial lane alignment sequence (ila) is never scrambled. scrambling can be enabled by setting scr ( jesd204b control register (address = 0x204) [reset = 0x02] ). 7.3.6.3 link layer the link layer serves multiple purposes in jesd204b, including establishing the code boundaries ( code group synchronization (cgs) ), initializing the link ( initial lane alignment sequence (ilas) ), encoding the data ( 8b/10b encoding ) and monitoring the health of the link ( frame and multiframe monitoring ). 7.3.6.3.1 code group synchronization (cgs) the first step in initializing the jesd204b link, after sysref is processed, is to achieve code group synchronization. the receiver first asserts the sync signal when ready to initialize the link. the transmitter responds to the request by sending a stream of k28.5 characters. the receiver then aligns its character clock to the k28.5 character sequence. code group synchronization is achieved after receiving four k28.5 characters successfully. the receiver deasserts sync on the next local multi-frame clock (lmfc) edge after cgs is achieved and waits for the transmitter to start the initial lane alignment sequence. 7.3.6.3.2 initial lane alignment sequence (ilas) after the transmitter sees the sync signal deassert it waits until its next lmfc edge to start sending the initial lane alignment sequence. the ilas consists of four multiframes each containing a predetermined sequence. the receiver looks for the start of the ilas to determine the frame and multiframe boundaries. as the ilas reaches the receiver for each lane, the lane starts to buffer its data until all receivers have received the ilas and subsequently release the ilas from all lanes at the same time in order to align the lanes. the second multiframe of the ilas contains configuration parameters for the jesd204b that can be used by the receiver to verify that the transmitter and receiver configurations match.
58 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.6.3.3 8b/10b encoding the data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across the link using 8b/10b encoding. 8b/10b encoding provides dc balance for ac coupling of the serdes links and a sufficient number of edge transitions for the receiver to reliably recover the data clock. 8b/10b also provides some amount of error detection where a single bit error in a character will likely result in either not being able to find the 10-bit character in the 8b/10b decoder lookup table or incorrect character disparity. 7.3.6.3.4 frame and multiframe monitoring adc12dj3200 supports frame and multiframe monitoring for verifying the health of the jesd204b link. if the last octet of a frame matches the last octet of the previous frame, then the second frame's last octet is replaced with a /f/ (/k28.7/) character. if the second frame is the last frame of a multiframe then a /a/ (/k28.3/) character is used instead. when scrambling is enabled, if the last octet of a frame is 0xfc then the transmitter replaces it with a /f/ (/k28.7/) character. with scrambling, if the last octet of a multiframe is 0x7c then the transmitter replaces it with a /a/ (/k28.3/) character. when the receiver sees a /f/ or /a/ character, it checks to see if it occurs at the end of a frame or multiframe, and replaces it with the appropriate data character. the receiver can report an error if the alignment characters occur in the incorrect place and trigger a link realignment. 7.3.6.4 physical layer the jesd204b physical layer consists of a current mode logic (cml) output driver and receiver. the receiver consists of a clock detection and recovery (cdr) unit to extract the data clock from the serialized data stream and may contain an equalizer to correct for the low pass response of the physical transmission channel. likewise, the transmitter may contain pre-equalization to account for frequency dependent losses across the channel. the total reach of the serdes links depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error performance. the serdes lanes do not have to be matched in length as the receiver will align the lanes during the initial lane alignment sequence. 7.3.6.4.1 serdes pre-emphasis adc12dj3200 high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis in order to compensate for the low pass response of the transmission channel. configurable pre-emphasis settings allow the output drive waveform to be optimized for different pcb materials and signal transmission distances. the pre-emphasis setting is adjusted through the serializer pre-emphasis setting ser_pe ( serializer pre- emphasis control register (address = 0x048) [reset = 0x00] ). higher values will increase the pre-emphasis to compensate for more lossy pcb materials. this adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. the pre-emphasis setting should be adjusted to optimize the eye-opening for the specific hardware configuration and line rates needed. 7.3.6.5 jesd204b enable the jesd204b interface must be disabled through jesd_en ( jesd204b enable register (address = 0x200) [reset = 0x01] ) while any of the other jesd204b parameters are being changed. while jesd_en is set to 0 the block is held in reset and the serializers are powered down. the clocks for this section are also gated off to further save power. when the parameters have been set as desired the jesd204b block can be enabled (jesd_en is set to 1). 7.3.6.6 multi-device synchronization and deterministic latency jesd204b subclass 1 outlines a method to achieve deterministic latency across the serial link. if two devices achieve the same deterministic latency then they can be considered synchronized. this latency must be achieved from system startup to startup to be deterministic. there are two key requirements to achieve deterministic latency. the first is proper capture of sysref for which adc12dj3200 provides a number of features to simplify this requirement at giga-sample clock rates (see sysref capture for multi-device synchronization and deterministic latency for more information). the second requirement is to choose a proper elastic buffer release point in the receiver. since adc12dj3200 is an adc it is the transmitter (tx) in the jesd204b link and the logic device will be the receiver (rx). the elastic buffer is the key block for achieving deterministic latency. it does so by absorbing variations in the propagation delays of the serialized data as it travels from the transmitter to the receiver. a proper release point is one that provides sufficient margin against variations in the delays. an incorrect release point will result in a latency
59 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated variation of one lmfc period. choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an lmfc edge, and the total expected delay variation for all devices. with this information the region of invalid release points within the lmfc period can be defined, which stretches from the minimum to maximum delay for all lanes. essentially, the designer must guarantee that the data for all lanes arrives at all devices before the release point occurs. it is easier to demonstrate this requirement by using a timing diagram as illustrated in figure 83 . here, the data for two adcs is shown. the second adc has a longer routing distance (t pcb ) and results in a longer link delay. first, the invalid region of the lmfc period is marked off as determined by the data arrival times for all devices. then, the release point is set by using the release buffer delay (rbd) parameter to shift the release point an appropriate number of frame clocks from the lmfc edge so that it occurs within the valid region of the lmfc cycle. in the case of figure 2, the lmfc edge (rbd = 0) is a good choice for the release point due to sufficient margin on each side. figure 83. definition of valid region of lmfc for elastic buffer release point selection note that the tx and rx lmfcs do not necessarily need to be phase aligned, but knowledge of their phase is important for proper elastic buffer release point selection. also, the elastic buffer release point occurs within every lmfc cycle, but the buffers only release once all lanes have arrived. therefore, the total link delay can exceed a single lmfc period. see jesd204b multi-device synchronization: breaking down the requirements for more information. 7.3.6.7 operation in subclass 0 systems the adc12dj3200 can operate with subclass 0 compatibility provided that multi-adc synchronization and deterministic latency are not required. with those limitations the device can operate without the application of sysref. the internal local multi-frame clock will be automatically self-generated with unknown timing. sync will be used as normal to initiate cgs and ila. 7.3.7 alarm monitoring a number of built in alarms are available to monitor internal events. several types of alarms/upsets are detected by this feature: 1. serializer pll not locked 2. jesd204b link not transmitting data (not in the data transmission state) 3. sysref caused internal clocks to be realigned 4. an upset that impacts the nco 5. an upset that impacts the internal clocks when an alarm occurs, a bit for each specific alarm is set in alm_status. each alarm bit remains set until the host system writes a 1 to clear it. if the alarm type is not masked (see alm_mask), then the alarm is also indicated by the alarm register. the calstat output pin can be configured as an alarm output that will go high when an alarm occurs. see cal_status_sel. tx lmfc rx lmfc adc 1 data propagation t tx t pcb t rx-deser time adc 2 data propagation t tx t pcb invalid region of lmfc valid region of lmfc nominal link delay (arrival at elastic buffer) link delay variation choose lmfc edge as release point (rbd = 0) release point margin t rx-deser
60 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.7.1 nco upset detection the nco_alm register bit indicates if the nco in channel a or b may have been upset. the nco phase accumulators in channel a are continuously compared to channel b. if they differ for even one clock cycle, the nco_alm register bit is set and remains set until cleared by the host system by writing a 1. this feature requires the phase and frequency words for each nco accumulator in ddc a (phaseax, freqax) to be set to the same values as the nco accumulators in ddc b (phasebx, freqbx). for example, phasea0 must be the same as phaseb0 and freqa0 must be the same as freqb0, however phasea1 can be set to a different value than phasea0. this ultimate reduces the number of nco frequencies available for phase coherent frequency hopping from four to two for each ddc. note that ddc b can use a different nco frequency than ddc a by setting the ncob[1:0] pins to a different value than ncoa[1:0]. this detection is only valid after the ncos have been synchronized by either sysref or the start of the ila sequence (as determined by nco_sync). for nco upset detection to work properly, follow this usage model: 1. program jesd_en=0 2. ensure the part is configured to utilize both channels (pd_ach=0, pd_bch=0) 3. select a jmode that utilizes the nco 4. program all nco frequencies and phases the same for channel a and b, for example freqa0=freqb0, freqa1=freqb1, freqa2=freqb2, freqa3=freqb3). 5. if desired, utilize the cmode and csel registers or the ncoa[1:0] and ncob[1:0] pins to choose a unique frequency for channel a and channel b 6. program jesd_en=1 7. synchronize the ncos (using the ila or using sysref). see nco_sync register. 8. write a ? 1 ? to the nco_alm register bit to clear it 9. monitor the nco_alm status bit or the calstat output pin if cal_status_sel is properly configured 10. if the frequency or phase registers are changed while the nco is enabled, the ncos can get out of synchronization. repeat steps 7-9. 11. if the device enters and exits global power down, repeat steps 7-9. 7.3.7.2 clock upset detection the clk_alm register bit indicates if the internal clocks may have been upset. the clocks in channel a are continuously compared to channel b. if they differ for even one devclk/2 cycle, the clk_alm register bit is set and remains set until cleared by the host system by writing a ? 1 ? . for the clk_alm register bit to function properly, follow this usage model: 1. program jesd_en=0 2. ensure the part is configured to utilize both channels (pd_ach=0, pd_bch=0) 3. program jesd_en=1 4. write clk_alm=1 to clear clk_alm 5. monitor the clk_alm status bit or the calstat output pin if cal_status_sel is properly configured 6. when exiting global power-down (via mode or the pd pin), the clk_alm status bit may be set and should be cleared by writing a '1' to clk_alm 7.3.8 temperature monitoring diode a built-in thermal monitoring diode is made available on the tdiode+ and tdiode ? pins. this diode facilitates temperature monitoring and characterization of the device in higher ambient temperature environments. while the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode voltage slope provided in electrical characteristics - dc specifications . offset measurement should be done with the device unpowered or with the pd pin asserted to minimize device self-heating. pd pin should be asserted only long enough to take the offset measurement. recommended monitoring ics include the lm95233 device and similar remote-diode temperature monitoring products from texas instruments.
61 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.9 analog reference voltage the reference voltage for adc12dj3200 is derived from an internal bandgap reference. a buffered version of the reference voltage is available at the bg pin for user convenience. this output has an output-current capability of 100 a. the bg output must be buffered if more current is required. no provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register settings. in unique cases, the va11 supply voltage can act as the reference voltage by setting bg_bypass ( internal reference bypass register (address = 0x038) [reset = 0x00] ). 7.4 device functional modes adc12dj3200 can be configured to operate in a number of functional modes. these modes are described in this section. 7.4.1 dual channel mode adc12dj3200 can be used as a dual channel adc where the sampling rate is equal to the clock frequency (f s = f clk ) provided at the clk+ and clk- pins. the two inputs, ain+/- and bin+/-, serve as the respective inputs for each channel in this mode. this mode is chosen simply by setting jmode to the appropriate setting for the desired configuration as described in table 18 . the analog inputs can be swapped by setting dual_input ( input mux control register (address = 0x060) [reset = 0x01] ) 7.4.2 single channel mode (des mode) adc12dj3200 can also be used as a single channel adc where the sampling rate is equal to two times the clock frequency (f s = 2xf clk ) provided at the clk+ and clk ? pins. this mode effectively interleaves the two adc channels together to form a single channel adc at twice the sampling rate. this mode is chosen simply by setting jmode to the appropriate setting for the desired configuration as described in table 18 . either analog input, ina+/ ? or inb+/ ? , can serve as the input to the adc, however ina+/ ? is recommended for best performance. the analog input can be selected using single_input ( input mux control register (address = 0x060) [reset = 0x01] ). the digital down-converters cannot be used in single channel mode. note in single channel mode it is strongly recommended that ina+/ ? be used as the input to the adc for optimized performance. 7.4.3 jesd204b modes adc12dj3200 can be programmed as a single channel or dual channel adc , with or without decimation, and a number jesd204b output formats. table 16 summarizes the basic operating mode configuration parameters and whether they are user configured or derived. note power down of the high speed data outputs (da0+/ ? ... da7+/ ? , db0+/ ? ... db7+/ ? ) for extended times may reduce performance of the output serializers, especially at high data rates. please see note beneath recommended operating conditions for more information. table 16. adc12dj3200 operating mode configuration parameters parameter description user configured or derived value jmode jesd204b operating mode, automatically derives the rest of the jesd204b parameters, single channel or dual channel mode and the decimation factor user set by jmode ( jesd204b mode register (address = 0x201) [reset = 0x02] ) d decimation factor derived see table 18 des 1 = single channel mode, 0 = dual channel mode derived see table 18
62 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) table 16. adc12dj3200 operating mode configuration parameters (continued) parameter description user configured or derived value r number of bits transmitted per lane per devclk cycle. the jesd204b linerate is the devclk frequency times r. this parameter sets the serdes pll multiplication factor or controls bypassing of the serdes pll. derived see table 18 links number of jesd204b links used derived see table 18 k number of frames per multi- frame user configured set by km1 ( jesd204b k parameter register (address = 0x202) [reset = 0x1f] ), see allowed values in table 18 there are a number of parameters required to define the jesd204b format, all of which are sent across the link during the initial lane alignment sequence. in the adc12dj3200, most of the parameters are automatically derived based on the selected jmode; however, a few are configured by the user. these parameters are described in table 17 . table 17. jesd204b initial lane alignment sequence parameters parameter description user configured or derived value adjcnt lmfc adjustment amount (not applicable) derived always 0 adjdir lmfc adjustment direction (not applicable) derived always 0 bid bank id derived always 0 cf number of control words per frame derived always 0 cs control bits per sample derived always set to 0 in ilas, see table 18 for actual usage did device identifier, used to identify the link user set by did ( jesd204b did parameter register (address = 0x206) [reset = 0x00] ), see table 19 f number of octets (bytes) per frame (per lane) derived see table 18 hd high density format (samples split between lanes) derived always 0 jesdv jesd204 standard revision derived always 1 k number of frames per multi- frame user set by km1 register, jesd204b k parameter register (address = 0x202) [reset = 0x1f] l number of serial output lanes per link derived see table 18 lid lane identifier for each lane derived see table 19 m number of converters used to determine lane bit packing; may not match number of adc channels in the device derived see table 18 n sample resolution (before adding control and tail bits) derived see table 18 n' bits per sample after adding control and tail bits derived see table 18 s number of samples per converter (m) per frame derived see table 18 scr scrambler enabled user set by scr register
63 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 17. jesd204b initial lane alignment sequence parameters (continued) parameter description user configured or derived value subclassv device subclass version derived always 1 res1 reserved field 1 derived always 0 res2 reserved field 2 derived always 0 chksum checksum for ilas checking (sum of all above parameters modulo 256) derived computed based on above parameters configuring the adc12dj3200 is made easy by use of a single configuration parameter called jmode ( jesd204b mode register (address = 0x201) [reset = 0x02] ). using table 18 , the correct jmode value can be found for the desired operating mode. the modes shown in table 18 are the only available operating modes. the table also gives a range and allowable step size for the k parameter (set by km1, see jesd204b k parameter register (address = 0x202) [reset = 0x1f] ), which sets the multi-frame length in number of frames.
adc12dj3200 slvsd97 ? june 2017 www.ti.com 64 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) m equals l in these modes to allow the samples to be sent in time-order over l lanes. the m parameter does not represent the actual number of converters. the m sample streams from each link should be interleaved in the receiver to produce the correct sample data. see mode diagrams for more details. (2) cs is always reported as 0 in the initial lane alignment sequence (ilas) for adc12dj3200. table 18. adc12dj3200 operating modes adc12dj3200 operating mode user specified parameter derived parameters input clock range (mhz) jmode k [min:step:max] d des links n cs n ? l (per link) m (per link) f s r (fbit/fclk) 12-bit, single channel, 8 lanes 0 3:1:32 1 1 2 12 0 12 4 4 (1) 8 5 4 800-3200 12-bit, single channel, 16 lanes 1 3:1:32 1 1 2 12 0 12 8 8 (1) 8 5 2 800-3200 12-bit, dual channel, 8 lanes 2 3:1:32 1 0 2 12 0 12 4 4 (1) 8 5 4 800-3200 12-bit, dual channel, 16 lanes 3 3:1:32 1 0 2 12 0 12 8 8 (1) 8 5 2 800-3200 8-bit, single channel, 4 lanes 4 18:2:32 1 1 2 8 0 8 2 1 1 2 5 800-2560 8-bit, single channel, 8 lanes 5 18:2:32 1 1 2 8 0 8 4 1 1 4 2.5 800-3200 8-bit, dual channel, 4 lanes 6 18:2:32 1 0 2 8 0 8 2 1 1 2 5 800-2560 8-bit, dual channel, 8 lanes 7 18:2:32 1 0 2 8 0 8 4 1 1 4 2.5 800-3200 reserved 8 - - - - - - - - - - - - - 15-bit, real data, decimate-by-2, 8 lanes 9 9:1:32 2 0 2 15 1 (2) 16 4 1 2 4 2.5 800-3200 15-bit, decimate-by-4, 4 lanes 10 9:1:32 4 0 2 15 1 (2) 16 2 2 2 1 5 800-2560 15-bit, decimate-by-4, 8 lanes 11 9:1:32 4 0 2 15 1 (2) 16 4 2 2 2 2.5 800-3200 12-bit, decimate-by-4, 16 lanes 12 3:1:32 4 0 2 12 0 12 8 8 (1) 8 5 1 1000-3200 15-bit, decimate-by-8, 2 lanes 13 5:1:32 8 0 2 15 1 (2) 16 1 2 4 1 5 800-2560 15-bit, decimate-by-8, 4 lanes 14 9:1:32 8 0 2 15 1 (2) 16 2 2 2 1 2.5 800-3200 15-bit, decimate-by-16, 1 lane 15 3:1:32 16 0 1 15 1 (2) 16 1 4 8 1 5 800-2560 15-bit, decimate-by-16, 2 lanes 16 5:1:32 16 0 2 15 1 (2) 16 1 2 4 1 2.5 800-3200 8-bit, single channel, 16 lanes 17 18:2:32 1 1 2 8 0 8 8 1 1 8 1.25 800-3200 8-bit, dual channel, 16 lanes 18 18:2:32 1 0 2 8 0 8 8 1 1 8 1.25 800-3200
65 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated adc12dj3200 has a total of sixteen high-speed output drivers which are grouped into two eight lane jesd204b links. most of the operating modes use two links with up to eight lanes per link. the lanes and their derived configuration parameters are described in table 19 . for a specified jmode, the lowest indexed lanes for each link are used while the higher indexed lanes for each link are automatically powered down. always route the lowest indexed lanes to the logic device. table 19. adc12dj3200 lane assignment and parameters device pin designation link did (user configured) lid (derived) da0+/ ? a set by did ( jesd204b did parameter register (address = 0x206) [reset = 0x00] ), the effective did is equal to the did register setting (did) 0 da1+/ ? 1 da2+/ ? 2 da3+/ ? 3 da4+/ ? 4 da5+/ ? 5 da6+/ ? 6 da7+/ ? 7 db0+/ ? b set by did ( jesd204b did parameter register (address = 0x206) [reset = 0x00] ), the effective did is equal to the did register setting plus 1 (did+1) 0 db1+/ ? 1 db2+/ ? 2 db3+/ ? 3 db4+/ ? 4 db5+/ ? 5 db6+/ ? 6 db7+/ ? 7 7.4.3.1 jesd204b output data formats output data is formatted in a specific optimized fashion for each jmode setting. when the ddc is not used (decimation = 1) the 12-bit offset binary values are mapped into octets. for the ddc mode the 16-bit values (15- bit complex data plus 1 over-range bit) are mapped into octets. the following tables show the specific mapping formats for a single frame. in all mappings the tail bits (t) are 0 (zero). in the tables below, the single channel format samples are defined as sn, where n is the sample number within the frame. in the dual channel real output formats (ddc bypass and dec-by-2), the samples are defined as an and bn, where an are samples from channel a and bn are samples from channel b. in the complex output formats (dec-by-4, dec-by-8, dec-by-16), the samples are defined as ain, aqn, bin and bqn, where ain and aqn are the in-phase and quadrature-phase samples of channel a and bin and bqn are the in-phase and quadrature-phase samples of channel b. all samples are formatted as msb first, lsb last.
66 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 20. jmode 0 (12-bit, dec-by-1, single channel, 8 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 s0 s8 s16 s24 s32 t da1 s2 s10 s18 s26 s34 t da2 s4 s12 s20 s28 s36 t da3 s6 s14 s22 s30 s38 t db0 s1 s9 s17 s25 s33 t db1 s3 s11 s19 s27 s35 t db2 s5 s13 s21 s29 s37 t db3 s7 s15 s23 s31 s39 t table 21. jmode 1 (12-bit, dec-by-1, single channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 s0 s16 s32 s48 s64 t da1 s2 s18 s34 s50 s66 t da2 s4 s20 s36 s52 s68 t da3 s6 s22 s38 s54 s70 t da4 s8 s24 s40 s56 s72 t da5 s10 s26 s42 s58 s74 t da6 s12 s28 s44 s60 s76 t da7 s14 s30 s46 s62 s78 t db0 s1 s17 s33 s49 s65 t db1 s3 s19 s35 s51 s67 t db2 s5 s21 s37 s53 s69 t db3 s7 s23 s39 s55 s71 t db4 s9 s25 s41 s57 s73 t db5 s11 s27 s43 s59 s75 t db6 s13 s29 s45 s61 s77 t db7 s15 s31 s47 s63 s79 t table 22. jmode 2 (12-bit, dec-by-1, dual channel, 8 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 a0 a4 a8 a12 a16 t da1 a1 a5 a9 a13 a17 t da2 a2 a6 a10 a14 a18 t da3 a3 a7 a11 a15 a19 t db0 b0 b4 b8 b12 b16 t db1 b1 b5 b9 b13 b17 t db2 b2 b6 b10 b14 b18 t db3 b3 b7 b11 b15 b19 t
67 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 23. jmode 3 (12-bit, dec-by-1, dual channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 a0 a8 a16 a24 a32 t da1 a1 a9 a17 a25 a33 t da2 a2 a10 a18 a26 a34 t da3 a3 a11 a19 a27 a35 t da4 a4 a12 a20 a28 a36 t da5 a5 a13 a21 a29 a37 t da6 a6 a14 a22 a30 a38 t da7 a7 a15 a23 a31 a39 t db0 b0 b8 b16 b24 b32 t db1 b1 b9 b17 b25 b33 t db2 b2 b10 b18 b26 b34 t db3 b3 b11 b19 b27 b35 t db4 b4 b12 b20 b28 b36 t db5 b5 b13 b21 b29 b37 t db6 b6 b14 b22 b30 b38 t db7 b7 b15 b23 b31 b39 t table 24. jmode 4 (8-bit, dec-by-1, single channel, 4 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 db0 s1 db1 s3 table 25. jmode 5 (8-bit, dec-by-1, single channel, 8 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 da2 s4 da3 s6 db0 s1 db1 s3 db2 s5 db3 s7 table 26. jmode 6 (8-bit, dec-by-1, dual channel, 4 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 db0 b0 db1 b1
68 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 27. jmode 7 (8-bit, dec-by-1, dual channel, 8 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 da2 a2 da3 a3 db0 b0 db1 b1 db2 b2 db3 b3 table 28. jmode 9 (15-bit, dec-by-2, dual channel, 8 lanes) octet 0 1 nibble 0 1 2 3 da0 a0 da1 a1 da2 a2 da3 a3 db0 b0 db1 b1 db2 b2 db3 b3 table 29. jmode 10 (15-bit, dec-by-4, dual channel, 4 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 aq0 db0 bi0 db1 bq0 table 30. jmode 11 (15-bit, dec-by-4, dual channel, 8 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 ai1 da2 aq0 da3 aq1 db0 bi0 db1 bi1 db2 bq0 db3 bq1
69 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 31. jmode 12 (12-bit, dec-by-4, dual channel, 16 lanes) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 ai0 ai4 ai8 ai12 ai16 t da1 aq0 aq4 aq8 aq12 aq16 t da2 ai1 ai5 ai9 ai13 ai17 t da3 aq1 aq5 aq9 aq13 aq17 t da4 ai2 ai6 ai10 ai14 ai18 t da5 aq2 aq6 aq10 aq14 aq218 t da6 ai3 ai7 ai11 ai15 ai19 t da7 aq3 aq7 aq11 aq15 aq19 t db0 bi0 bi4 bi8 bi12 bi16 t db1 bq0 bq4 bq8 bq12 bq16 t db2 bi1 bi5 bi9 bi13 bi17 t db3 bq1 bq5 bq9 bq13 bq17 t db4 bi2 bi6 bi10 bi14 bi18 t db5 bq2 bq6 bq10 bq14 bq218 t db6 bi3 bi7 bi11 bi15 bi19 t db7 bq3 bq7 bq11 bq15 bq19 t table 32. jmode 13 (15-bit, dec-by-8, dual channel, 2 lanes) octet 0 1 2 3 nibble 0 1 2 3 4 5 6 7 da0 ai0 aq0 db0 bi0 bq0 table 33. jmode 14 (15-bit, dec-by-8, dual channel, 4 lanes) octet 0 1 nibble 0 1 2 3 da0 ai0 da1 aq0 db0 bi0 db1 bq0 table 34. jmode 15 (15-bit, dec-by-16, dual channel, 1 lane) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 ai0 aq0 bi0 bq0 table 35. jmode 16 (15-bit, dec-by-16, dual channel, 2 lanes) octet 0 1 2 3 nibble 0 1 2 3 4 5 6 7 da0 ai0 aq0 db0 bi0 bq0
70 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 36. jmode 17 (8-bit, dec-by-1, single channel, 16 lanes) octet 0 nibble 0 1 da0 s0 da1 s2 da2 s4 da3 s6 da4 s8 da5 s10 da6 s12 da7 s14 db0 s1 db1 s3 db2 s5 db3 s7 db4 s9 db5 s11 db6 s13 db7 s15 table 37. jmode 18 (8-bit, dec-by-1, dual channel, 16 lanes) octet 0 nibble 0 1 da0 a0 da1 a1 da2 a2 da3 a3 da4 a4 da5 a5 da6 a6 da7 a7 db0 b0 db1 b1 db2 b2 db3 b3 db4 b4 db5 b5 db6 b6 db7 b7 7.4.3.2 dual ddc and redundant data mode when operating in dual channel mode the data from one channel can be routed to both digital down-converter blocks by using dig_bind_a or dig_bind_b ( digital channel binding register (address = 0x216) [reset = 0x02] ). this enables down-conversion of two separate captured bands from a single adc channel. the second adc can be powered down in this mode by setting pd_ach or pd_bch ( device configuration register (address = 0x002) [reset = 0x00] ).
71 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated additionally, dig_bind_a or dig_bind_b can be used to provide redundant data to separate digital processors by routing data from one adc channel to both jesd204b links. redundant data mode is available for all jmode modes except for the single channel modes. both dual ddc mode and redundant data mode are demonstrated in figure 84 where the data for adc channel a is routed to both ddcs and then transmitted to a single processor or two processors (for redundancy). figure 84. dual ddc mode or redundant data mode for channel a 7.4.4 power down modes note power down of the high speed data outputs (da0+/ ? ... da7+/ ? , db0+/ ? ... db7+/ ? ) for extended times may reduce performance of the output serializers, especially at high data rates. please see note beneath recommended operating conditions for more information. the pd input pin allows the adc12dj3200 devices to be entirely powered down. power down can also be controlled by mode ( device configuration register (address = 0x002) [reset = 0x00] ). the serial data output drivers are disabled when pd is high. when the device returns to normal operation, the jesd204 link must be re-established, and the adc pipeline contain meaningless information so the system must wait a sufficient time for the data to be flushed. if power down for power savings is desired the system should power down the supply voltages regulators for va19, va11 and vd11 rather than make use of the pd input or mode settings. 7.4.5 test modes a number of device test modes are available. these modes insert known patterns of information into the device data path for assistance with system debug, development, or characterization. 7.4.5.1 serializer test-mode details test modes are enabled by setting jtest ( jesd204b test pattern control register (address = 0x205) [reset = 0x00] ) to the desired test mode. each test mode is described in detail in the following sections. regardless of the test mode, the serializer outputs are powered up based on jmode. the test modes should only be enabled while the jesd204b link is disabled. mux dig_bind_a = 0 adc channel a adc channel b jesd204b link a (da0-da7) ddc a mux jmode ddc bypass mux jesd204b link b (db0-db7) ddc b mux jmode ddc bypass dig_bind_b = 0 copyright ? 2016, texas instruments incorporated
72 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 85. test-mode insertion points 7.4.5.2 prbs test modes the prbs test modes bypass the 8b/10b encoder. these test modes produce pseudo-random bit streams that comply with the itu-t o.150 specification. these bit streams are used with lab test equipment that can self- synchronize to the bit pattern and therefore the initial phase of the pattern is not defined. the sequences are defined by a recursive equation. for example, the prbs7 sequence is defined as shown in equation 10 . y[n] = y[n ? 6] y[n ? 7] where bit n is the xor of bit [n ? 6] and bit [n ? 7] which are previously transmitted bits (10) table 38. pbrs mode equations prbs test mode sequence sequence length (bits) prbs7 y[n] = y[n ? 6] y[n ? 7] 127 prbs15 y[n] = y[n ? 14] y[n ? 15] 32767 prbs23 y[n] = y[n ? 18] y[n ? 23] 8388607 the initial phase of the pattern is unique for each lane. 7.4.5.3 ramp test mode in the ramp test mode, the jesd204b link layer operates normally, but the transport layer is disabled and the input from the formatter is ignored. after the ila sequence, each lane transmits an identical octet stream that increments from 0x00 to 0xff and repeats. 7.4.5.4 short and long transport test mode jesd204b defines both short and long transport test modes to verify that the transport layers in the transmitter and receiver are operating correctly. adc12dj3200 has three different transport layer test patterns depending on the n' value of the specified jmode ( table 18 ). 7.4.5.4.1 short transport test pattern short transport test patterns send a predefined octet format that repeats every frame. in the adc12dj32000, all of the jmode configurations that have an n' value of 8 or 12 use the short transport test pattern. table 39 and table 40 define the short transport test patterns for n' values of 8 and 12. all applicable lanes are shown, however only the enabled lanes (lowest indexed) for the configured jmode are used. table 39. short transport test pattern for n ' = 8 modes (length = 2 frames) frame: 0 1 da0 0x00 0xff adc jesd204b transport layer scrambler (optional) jesd204b link layer jesd204b tx 8b/10b encoder adc jesd204b block long/short transport octet ramp test mode enable repeated ila modified rpat test mode enable prbs d21.5 k28.5 serial outputs high/low test mode enable active lanes and serial rates set by jmode copyright ? 2016, texas instruments incorporated
73 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 39. short transport test pattern for n ' = 8 modes (length = 2 frames) (continued) frame: 0 1 da1 0x01 0xfe da2 0x02 0xfd da3 0x03 0xfc db0 0x00 0xff db1 0x01 0xfe db2 0x02 0xfd db3 0x03 0xfc table 40. short transport test pattern for n ' = 12 modes (length = 1 frame) octet 0 1 2 3 4 5 6 7 nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da0 0xf01 0xf02 0xf03 0xf04 0xf05 t da1 0xe11 0xe12 0xe13 0xe14 0xe15 t da2 0xd21 0xd22 0xd23 0xd24 0xd25 t da3 0xc31 0xc32 0xc33 0xc34 0xc35 t da4 0xb41 0xb42 0xb43 0xb44 0xb45 t da5 0xa51 0xa52 0xa53 0xa54 0xa55 t da6 0x961 0x962 0x963 0x964 0x965 t da7 0x871 0x872 0x873 0x874 0x875 t db0 0xf01 0xf02 0xf03 0xf04 0xf05 t db1 0xe11 0xe12 0xe13 0xe14 0xe15 t db2 0xd21 0xd22 0xd23 0xd24 0xd25 t db3 0xc31 0xc32 0xc33 0xc34 0xc35 t db4 0xb41 0xb42 0xb43 0xb44 0xb45 t db5 0xa51 0xa52 0xa53 0xa54 0xa55 t db6 0x961 0x962 0x963 0x964 0x965 t db7 0x871 0x872 0x873 0x874 0x875 t 7.4.5.4.2 long transport test pattern the long-transport test mode is used in all of the jmode modes where n' equals 16. patterns are generated in accordance with the jesd204b standard and are different for each output format as defined in table 18 . the rules for the pattern are defined below. the length of the test pattern is given by equation 11 . the long transport test pattern is the same for link a and link b, where dax lanes belong to link a and dbx lanes belong to link b. long test pattern length (frames) = k * ceil((m*s+2) / k) (11) ? sample data: ? frame 0: each sample contains n bits, with all samples set to the converter id (cid) plus 1 (cid + 1). cid is defined based on the converter number within the link; note that two links are used in all modes except jmode 15. within a link, the converters are numbered by channel (a or b) and in-phase (i) and quadrature-phase (q) and reset between links. for instance, in jmode 10, two links are used so channel a and b data is separated into separate links and the in-phase component for each channel has cid = 0 and the quadrature-phase component has cid = 1. in jmode 15, one link is used, so channel a and b are within the same link and ai has cid = 0, aq has cid = 1, bi has cid = 2, and bq has cid = 3. ? frame 1: each sample contains n bits, with each sample (for each converter) set as its individual sample id (sid) within the frame plus 1 (sid + 1) ? frame 2 +: each sample contains n bits, with the data set to 2 n ? 1 for all samples, for example if n is 15, then 2 n ? 1 = 16384 ? control bits (if cs > 0): ? frame 0 to m*s ? 1: the control bit belonging to sample mod(i,s) of converter floor(i,s) set to "1" and all others set to "0", where i is the frame index (i=0 is the first frame of the pattern). essentially, the control bit
74 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated "walks" from the lowest indexed sample to the highest indexed sample and from the lowest indexed converter to highest indexed converter, changing position every frame. ? frame m*s +: all control bits set to 0 table 41. example long transport test pattern - jmode = 10, k = 10 time pattern repeats octet num. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 da0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 da1 0x0004 0x0003 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 db0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 db1 0x0004 0x0003 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 frame n frame n + 1 frame n + 2 frame n + 3 frame n + 4 frame n + 5 frame n + 6 frame n + 7 frame n + 8 frame n + 9 frame n + 10 the pattern starts at the end of the initial lane alignment sequence (ilas) and repeats indefinitely as long as the link remains running. for more details see jesd204b, section 5.1.6.3. 7.4.5.5 d21.5 test mode in this test mode, the controller transmits a continuous stream of d21.5 characters (alternating 0s and 1s). 7.4.5.6 k28.5 test mode in this test mode, the controller transmits a continuous stream of k28.5 characters. 7.4.5.7 repeated ila test mode in this test mode, the jesd204b link layer operates normally, except that the ila sequence (ilas) repeats indefinitely instead of starting the data phase. whenever the receiver issues a synchronization request, the transmitter will initiate code group synchronization. upon completion of code group synchronization, the transmitter will repeatedly transmit the ila sequence. 7.4.5.8 modified rpat test mode a 12-octet repeating pattern is defined in incits tr-35-2004. the purpose of this pattern is to generate white spectral content for jesd204b compliance and jitter testing. table 42 lists the pattern before and after 8b10b encoding. table 42. modified rpat pattern values octet number dx.y notation 8-bit input to 8b10b encoder 20b output of 8b10b encoder (2 characters) 0 d30.5 0xbe 0x86ba6 1 d23.6 0xd7 2 d3.1 0x23 0xc6475 3 d7.2 0x47 4 d11.3 0x6b 0xd0e8d 5 d15.4 0x8f 6 d19.5 0xb3 0xca8b4 7 d20.0 0x14 8 d30.2 0x5e 0x7949e 9 d27.7 0xfb 10 d21.1 0x35 0xaa665 11 d25.2 0x59
75 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4.6 calibration modes and trimming adc12dj3200 has two calibration modes available, foreground calibration and background calibration. when foreground calibration is initiated the adcs are automatically taken offline and the output data becomes midcode (0x000 in 2's complement) while calibration is occurring. background calibration allows the adc to continue normal operation while the adc cores are calibrated in the background by swapping in a different adc core to take its place. additional offset calibration features are available in both foreground and background calibration modes. further, a number of adc parameters can be trimmed to optimize performance in a user's system. adc12dj3200 consists of a total of six sub-adcs, each referred to as a "bank", with two banks forming an adc core. the banks sample out of phase so that each adc core is two-way interleaved. the six banks form three adc cores, referred to as adc a, adc b and adc c. in foreground calibration mode, adc a samples ina+/ ? and adc b samples inb+/ ? in dual channel mode and both adc a and adc b sample ina+/ ? (or inb+/ ? ) in single channel mode. in background calibration modes, the third adc core, adc c, is swapped in periodically for adc a and adc b so that they can be calibrated without disrupting operation. figure 86 shows a diagram of the calibration system including labeling of the banks that make up each adc core. when calibration is performed the linearity, gain and offset voltage for each bank are calibrated to an internally generated calibration signal. the analog inputs can be driven during calibration, both foreground and background, except that when offset calibration (os_cal or bgos_cal) is used there should be no signals (or aliased signals) near dc for proper estimation of the offset (see offset calibration ). figure 86. adc12dj3200 calibration system block diagram in addition to calibration, a number of adc parameters are user controllable to allowing trimming for optimal performance. these include input offset voltage, adc gain, interleaving timing and input termination resistance. the default trim values are programmed at the factory to unique values for each device which are determined to be optimal at the test system's operating conditions. the user can read the factory programmed values from the trim registers and adjusted as desired. the register fields that control the trimming are labeled according to the adc a ina+ ina- inb+ inb- calibration signal calibration signal calibration signal bank 1 bank 0 adc c bank 3 bank 2 adc b bank 5 bank 4 calibration engine mux mux mux mux mux adc a output adc b output calibration engine calibration engine calibration engine calibration engine interleave interleave interleave copyright ? 2016, texas instruments incorporated
76 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated input that is being sampled (ina+/ ? or inb+/ ? ), the bank that is being trimmed or the adc core that is being trimmed. it is not expected that the user must change the trim values as operating conditions change, however optimal performance may be obtained by doing so. any custom trimming must be done on a per device basis due to process variations, meaning that there is no global optimal setting for all parts. see trimming for information about the available trim parameters and associated registers. 7.4.6.1 foreground calibration mode foreground calibration requires the adc to stop converting the analog input signals during the procedure. foreground calibration always runs on power up and the user must wait a sufficient time before programming the device to guarantee that the calibration is finished. foreground calibration can be initiated by triggering the calibration engine. the trigger source can be either the cal_trig pin or cal_soft_trig ( calibration software trigger register (address = 0x06c) [reset = 0x01] ) and is chosen by setting cal_trig_en ( calibration pin configuration register (address = 0x06b) [reset = 0x00] ). 7.4.6.2 background calibration mode background calibration mode allows the adc to continuously operate, with no interruption of data. this is accomplished by activating an extra adc core which is calibrated and then takes over operation for one of the other previously active adc cores. once that adc core is taken off-line it is then calibrated and can in turn take over to allow the next adc to be calibrated. this process operates continuously, ensuring the adc cores are always providing the optimum performance regardless of system operating condition changes. due to the additional active adc core, background calibration mode has increased power consumption in comparison to foreground calibration mode. the low-power background calibration (lpbg) mode discussed next provides reduced average power consumption in comparison with the standard background calibration mode. background calibration can be enabled by setting cal_bg ( calibration configuration 0 register (address = 0x062) [reset = 0x01] ). cal_trig_en should be set to 0 and cal_soft_trig should be set to 1. great care has been taken to minimize effects on converted data as the core switching process occurs, however, small brief glitches may still be seen on the converter data as the cores are swapped. please refer to the typical characteristic section of the datasheet for examples of the possible glitches in sine-wave and dc signals. 7.4.6.3 low-power background calibration (lpbg) mode low-power background calibration (lpbg) mode reduces the power-overhead of enabling additional adc cores. off-line cores are powered down until ready to be calibrated and put on-line. set lp_en=1 to enable the low- power background calibration feature. lp_sleep_dly is used to adjust the amount of time an adc sleeps before waking up for calibration (if lp_en=1 and lp_trig=0). lp_wake_dly sets how long the core is allowed to stabilize before calibration and being put on-line. lp_trig is used to select between an automatic switching process or one that is controlled by the user via cal_soft_trig or cal_trig. in this mode there is an increase in power consumption during the adc core calibration. the power consumption will roughly alternate between the power consumption in foreground calibration when the spare adc core is sleeping to the power consumption in background calibration when the spare adc is being calibrated. the power supply network should be designed to be able to handle the transient power requirements for this mode. 7.4.7 offset calibration foreground calibration and background calibration modes inherently calibrate the offsets of the adc cores, however the input buffers sits outside of the calibration loop and therefore their offsets are not calibrated by the standard calibration process. in both dual channel mode and single channel mode uncalibrated input buffer offsets result in a shift in the mid-code output (dc offset) with no input. further, in single channel mode uncalibrated input buffer offsets can result in a fixed spur at f s /2. a separate calibration is provided to correct the input buffer offsets.
77 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated there must be no signals at or near dc or aliased signals that fall at or near dc in order to properly calibration the offsets, requiring the system to guarantee this condition during normal operation or have the ability to mute the input signal during calibration. foreground offset calibration is enabled via cal_os and only performs the calibration once as part of the foreground calibration procedure. background offset calibration is enabled via cal_bgos and will continue to correct the offset as part of the background calibration routine to account for operating condition changes. when cal_bgos is set the system must guarantee that there are no dc or near dc signals or aliased signals that fall at or near dc during normal operation. offset calibration can be performed as a foreground operation when using background calibration by setting cal_os to 1 before setting cal_en, but it will not correct for variations as operating conditions change. the offset calibration correction uses the input offset voltage trim registers (see table 43 ) to correct the offset and therefore must not be written by the user when offset calibration is used. the user can read the calibrated values by reading the oadj_x_viny registers, where x is the adc core and y is the input (ina+/ ? or inb+/ ? ), after calibration is completed. the values should only be read when fg_done is read as 1 when using foreground offset calibration (cal_os = 1) and should not be read when using background offset calibration (cal_bgos = 1). 7.4.8 trimming the parameters that can be trimmed and the associated registers are summarized in table 43 . table 43. trim register descriptions trim parameter trim register notes bandgap reference bg_trim measure on bg output pin. input termination resistance rtrim_x where x = a for ina+/ ? or b for inb+/ ? ) device must be powered on with a clock applied. input offset voltage oadj_x_viny where x = adc core (a, b or c) and y = a for ina+/ ? or b for inb+/ ? ) a different trim value is allowed for each adc core (a, b or c) to allow more consistent offset performance in background calibration mode. ina+/ ? and inb+/ ? gain gain_trim_x where x = a for ina+/ ? or b for inb+/ ? ) fs_range_a and fs_range_b should be set to default values before trimming the input. fs_range_a and fs_range_b should be used to adjust the full scale input voltage. ina+/ ? and inb+/ ? full scale input voltage fs_range_x where x = a for ina+/ ? or b for inb+/ ? ) full scale input voltage adjustment for each input. the default value is effected by gain_trim_x (x = a or b). gain_trim_x should be trimmed with fs_range_x set to the default value. fs_range_x can then be used to trim the full scale input voltage. intra-adc core timing (bank timing) bx_time_y where x = bank number (0 ? 5) and y = 0 or ? 90 clock phase trims the timing between the two banks of an adc core (adc a, b or c) for two clock phases, either 0 or ? 90 . the ? 90 clock phase is used in single channel mode only. inter-adc core timing (dual channel mode) tadj_a, tadj_b, tadj_ca, tadj_cb the suffix letter (a, b, ca or cb) indicates the adc core that is being trimmed. ca indicates that this is the timing trim in background calibration mode for adc c when it is standing in for adc a, whereas cb is timing trim for adc c when it is standing in for adc b.
78 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 43. trim register descriptions (continued) trim parameter trim register notes inter-adc core timing (single channel mode) tadj_a_fg90, tadj_b_fg0, tadj_a_bg90, tadj_c_bg0, tadj_c_bg90, tadj_b_bg0 the middle letter (a, b or c) indicates the adc core that is being trimmed. fg indicates that it is a trim for foreground calibration while bg indicates background calibration. the suffix of 0 or 90 indicates the clock phase applied to the adc core. 0 indicates a 0 clock and is sampling in-phase with the clock input. 90 indicates a 90 clock and therefore is sampling out-of-phase with the clock input. these timings must be trimmed for optimal performance if the user prefers to use inb+/ ? in single channel mode. they are trimmed for ina+/ ? at the factory. 7.4.9 offset filtering the adc12dj3200 has an additional feature which can be enabled to reduce offset related interleaving spurs at fs/2 and fs/4 (single input mode only). offset filtering is enabled via cal_osfilt. the osfilt_bw and osfilt_soak parameters can be adjusted to tradeoff offset spur reduction with potential impact on information in the mission mode signal being processed. these two parameters should be set to the same value under most situations. the dc_restore setting is used to either retain or filter out all dc related content in the signal.
79 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5 programming 7.5.1 using the serial interface the serial interface is accessed using the following four pins: serial clock (sclk), serial-data in (sdi), serial-data out (sdo), and serial-interface chip-select ( scs). registers access is enabled through the scs pin. 7.5.1.1 scs this signal must be asserted low to access a register through the serial interface. setup and hold times with respect to the sclk must be observed. 7.5.1.2 sclk serial data input is accepted at the rising edge of this signal. sclk has no minimum frequency requirement. 7.5.1.3 sdi each register access requires a specific 24-bit pattern at this input. this pattern consists of a read-and-write (r/w) bit, register address, and register value. the data is shifted in msb first. setup and hold times with respect to the sclk must be observed (see timing requirements ). 7.5.1.4 sdo the sdo signal provides the output data requested by a read command. this output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles. each register access consists of 24 bits, as shown in figure 87 . the first bit is high for a read and low for a write. the next 15 bits are the address of the register that is to be written to. during write operations, the last 8 bits are the data written to the addressed register. during read operations, the last 8 bits on sdi are ignored, and, during this time, the sdo outputs the data from the addressed register. the serial protocol details are illustrated in figure 87 . figure 87. serial interface protocol - single read / write 7.5.1.5 streaming mode the serial interface supports streaming reads and writes. in this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. additional clock cycles of write or read data are immediately transferred, as long as the scs input is maintained in the asserted (logic low) state. the register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming transaction. the addr_asc bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). streaming mode can be disabled by setting the addr_hold bit ( user spi configuration register (address = 0x010) [reset = 0x00] ). the streaming mode transaction details are shown in figure 88 . sclk 1 24 single register access scs sdi command field data field sdo (read mode) data field high z high z 17 16 8 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w
80 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) figure 88. serial interface protocol - streaming read / write see the register maps section for detailed information regarding the registers. note the serial interface must not be accessed during calibration of the adc. accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. writing or reading the serial registers also reduces dynamic performance of the adc for the duration of the register access time. 7.6 register maps memory map address reset acronym type register name standard spi-3.0 (0x000 to 0x00f) 0x000 0x30 config_a r/w configuration a register 0x001 undefined reserved r reserved 0x002 0x00 device_config r/w device configuration register 0x003 0x03 chip_type r chip type register 0x004-0x005 0x0020 chip_id r chip id registers 0x006 0x0a chip_version r chip version register 0x007-0x00b undefined reserved r reserved 0x00c-0x00d 0x0451 vendor_id r vendor identification register 0x00e-0x00f undefined reserved r reserved user spi configuration (0x010 to 0x01f) 0x010 0x00 usr0 r/w user spi configuration register 0x011-0x01f undefined reserved r reserved miscellaneous analog registers (0x020 to 0x047) 0x020-0x028 undefined reserved r reserved 0x029 0x00 clk_ctrl0 r/w clock control register 0 0x02a 0x20 clk_ctrl1 r/w clock control register 1 0x02b undefined reserved r reserved 0x02c-0x02e undefined sysref_pos r sysref capture position register 0x02f undefined reserved r reserved 0x030-0x031 0xa000 fs_range_a r/w ina full scale range adjust register 0x032-0x033 0xa000 fs_range_b r/w inb full scale range adjust register 0x034-0x037 undefined reserved r reserved 0x038 0x00 bg_bypass r/w internal reference bypass register sclk 1 24 multiple register access scs sdi command field data field (write mode) sdo (read mode) data field high z 17 16 8 32 data field high z 25 data field (write mode) a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
81 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x039-0x03a undefined reserved r reserved 0x03b 0x00 tmstp_ctrl r/w tmstp+/- control register 0x03c-0x047 undefined reserved r reserved serializer registers (0x048 to 0x05f) 0x048 0x00 ser_pe r/w serializer pre-emphasis control register 0x049-0x05f undefined reserved r reserved calibration registers (0x060 to 0x0ff) 0x060 0x01 input_mux r/w input mux control register 0x061 0x01 cal_en r/w calibration enable register 0x062 0x01 cal_cfg0 r/w calibration configuration 0 register 0x063-0x069 undefined reserved r reserved 0x06a undefined cal_status r calibration status register 0x06b 0x00 cal_pin_cfg r/w calibration pin configuration register 0x06c 0x01 cal_soft_trig r/w calibration software trigger register 0x06d undefined reserved r reserved 0x06e 0x88 cal_lp r/w low-power background calibration register 0x06f undefined reserved r reserved 0x070 0x00 cal_data_en r/w calibration data enable register 0x071 undefined cal_data r/w calibration data register 0x072-0x079 undefined reserved r reserved 0x07a undefined gain_trim_a r/w channel a gain trim register 0x07b undefined gain_trim_b r/w channel b gain trim register 0x07c undefined bg_trim r/w band-gap reference trim register 0x07d undefined reserved r reserved 0x07e undefined rtrim_a r/w vina input resistor trim register 0x07f undefined rtrim_b r/w vinb input resistor trim register 0x080 undefined tadj_a_fg90 r/w timing adjustment for a-adc, single channel mode, foreground calibration register 0x081 undefined tadj_b_fg0 r/w timing adjustment for b-adc, single channel mode, foreground calibration register 0x082 undefined tadj_a_bg90 r/w timing adjustment for a-adc, single channel mode, background calibration register 0x083 undefined tadj_c_bg0 r/w timing adjustment for c-adc, single channel mode, background calibration register 0x084 undefined tadj_c_bg90 r/w timing adjustment for c-adc, single channel mode, background calibration register 0x085 undefined tadj_b_bg0 r/w timing adjustment for b-adc, single channel mode, background calibration register 0x086 undefined tadj_a r/w timing adjustment for a-adc, dual channel mode register 0x087 undefined tadj_ca r/w timing adjustment for c-adc acting for a-adc, dual channel mode register 0x088 undefined tadj_cb r/w timing adjustment for c-adc acting for b-adc, dual channel mode register 0x089 undefined tadj_b r/w timing adjustment for b-adc, dual channel mode register 0x08a-0x08b undefined oadj_a_ina r/w offset adjustment for a-adc and ina register 0x08c-0x08d undefined oadj_a_inb r/w offset adjustment for a-adc and inb register 0x08e-0x08f undefined oadj_c_ina r/w offset adjustment for c-adc and ina register 0x090-0x091 undefined oadj_c_inb r/w offset adjustment for c-adc and inb register
82 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x092-0x093 undefined oadj_b_ina r/w offset adjustment for b-adc and ina register 0x094-0x095 undefined oadj_b_inb r/w offset adjustment for b-adc and inb register 0x096 undefined reserved r reserved 0x097 0x00 osfilt0 r/w offset filtering control 0 0x098 0x33 osfilt1 r/w offset filtering control 1 0x099-0x0ff undefined reserved r reserved adc bank registers (0x100 to 0x15f) 0x100-0x101 undefined reserved r reserved 0x102 undefined b0_time_0 r/w timing adjustment for bank 0 (0 clock) register 0x103 undefined b0_time_90 r/w timing adjustment for bank 0 (-90 clock) register 0x104-0x111 undefined reserved r reserved 0x112 undefined b1_time_0 r/w timing adjustment for bank 1 (0 clock) register 0x113 undefined b1_time_90 r/w timing adjustment for bank 1 (-90 clock) register 0x114-0x121 undefined reserved r reserved 0x122 undefined b2_time_0 r/w timing adjustment for bank 2 (0 clock) register 0x123 undefined b2_time_90 r/w timing adjustment for bank 2 (-90 clock) register 0x124-0x131 undefined reserved r reserved 0x132 undefined b3_time_0 r/w timing adjustment for bank 3 (0 clock) register 0x133 undefined b3_time_90 r/w timing adjustment for bank 3 (-90 clock) register 0x134-0x141 undefined reserved r reserved 0x142 undefined b4_time_0 r/w timing adjustment for bank 4 (0 clock) register 0x143 undefined b4_time_90 r/w timing adjustment for bank 4 (-90 clock) register 0x144-0x151 undefined reserved r reserved 0x152 undefined b5_time_0 r/w timing adjustment for bank 5 (0 clock) register 0x153 undefined b5_time_90 r/w timing adjustment for bank 5 (-90 clock) register 0x154-0x15f undefined reserved r reserved lsb control registers (0x160 to 0x1ff) 0x160 0x00 enc_lsb r/w lsb control bit output register 0x161-0x1ff undefined reserved r reserved jesd204b registers (0x200 to 0x20f) 0x200 0x01 jesd_en r/w jesd204b enable register 0x201 0x02 jmode r/w jesd204b mode (jmode) register 0x202 0x1f km1 r/w jesd204b k parameter register 0x203 0x01 jsync_n r/w jesd204b manual sync request register 0x204 0x02 jctrl r/w jesd204b control register 0x205 0x00 jtest r/w jesd204b test pattern control register 0x206 0x00 did r/w jesd204b did parameter register 0x207 0x00 fchar r/w jesd204b frame character register 0x208 undefined jesd_status r/w jesd204b / system status register 0x209 0x00 pd_ch r/w jesd204b channel power down 0x20a 0x00 jextra_a r/w jesd204b extra lane enable (link a) 0x20b 0x00 jextra_b r/w jesd204b extra lane enable (link b) 0x20c-0x20f undefined reserved r reserved digital down converter registers (0x210-0x2af) 0x210 0x00 ddc_cfg r/w ddc configuration register 0x211 0xf2 ovr_t0 r/w over-range threshold 0 register
83 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) memory map (continued) address reset acronym type register name 0x212 0xab ovr_t1 r/w over-range threshold 1 register 0x213 0x07 ovr_cfg r/w over-range configuration register 0x214 0x00 cmode r/w ddc configuration preset mode register 0x215 0x00 csel r/w ddc configuration preset select register 0x216 0x02 dig_bind r/w digital channel binding register 0x217-0x218 0x0000 nco_rdiv r/w rational nco reference divisor register 0x219 0x02 nco_sync r/w nco synchronization register 0x21a-0x21f undefined reserved r reserved 0x220-0x223 0xc0000000 freqa0 r/w nco frequency (ddc a preset 0) 0x224-0x225 0x0000 phasea0 r/w nco phase (ddc a preset 0) 0x226-0x227 undefined reserved r reserved 0x228-0x22b 0xc0000000 freqa1 r/w nco frequency (ddc a preset 1) 0x22c-0x22d 0x0000 phasea1 r/w nco phase (ddc a preset 1) 0x22e-0x22f undefined reserved r reserved 0x230-0x233 0xc0000000 freqa2 r/w nco frequency (ddc a preset 2) 0x234-0x235 0x0000 phasea2 r/w nco phase (ddc a preset 2) 0x236-0x237 undefined reserved r reserved 0x238-0x23b 0xc0000000 freqa3 r/w nco frequency (ddc a preset 3) 0x23c-0x23d 0x0000 phasea3 r/w nco phase (ddc a preset 3) 0x23e-0x23f undefined reserved r reserved 0x240-0x243 0xc0000000 freqb0 r/w nco frequency (ddc b preset 0) 0x244-0x245 0x0000 phaseb0 r/w nco phase (ddc b preset 0) 0x246-0x247 undefined reserved r reserved 0x248-0x24b 0xc0000000 freqb1 r/w nco frequency (ddc b preset 1) 0x24c-0x24d 0x0000 phaseb1 r/w nco phase (ddc b preset 1) 0x24e-0x24f undefined reserved r reserved 0x250-0x253 0xc0000000 freqb2 r/w nco frequency (ddc b preset 2) 0x254-0x255 0x0000 phaseb2 r/w nco phase (ddc b preset 2) 0x256-0x257 undefined reserved r reserved 0x258-0x25b 0xc0000000 freqb3 r/w nco frequency (ddc b preset 3) 0x25c-0x25d 0x0000 phaseb3 r/w nco phase (ddc b preset 3) 0x25e-0x296 undefined reserved r reserved 0x297 undefined spin_id r spin identification value 0x298-0x2af undefined reserved r reserved sysref calibration registers (0x2b0 to 0x2bf) 0x2b0 0x00 src_en r/w sysref calibration enable register 0x2b1 0x05 src_cfg r/w sysref calibration configuration register 0x2b2-0x2b4 undefined src_status r sysref calibration status 0x2b5-0x2b7 0x00 tad r/w devclk aperture delay adjustment register 0x2b8 0x00 tad_ramp r/w devclk timing adjust ramp control register 0x2b9-0x2bf undefined reserved r reserved alarm registers (0x2c0 to 0x2c2) 0x2c0 undefined alarm r alarm interrupt status register 0x2c1 0x1f alm_status r/w alarm status register 0x2c2 0x1f alm_mask r/w alarm mask register
84 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1 register descriptions 7.6.1.1 standard spi-3.0 (0x000 to 0x00f) table 44. standard spi-3.0 registers address reset acronym register name section 0x000 0x30 config_a configuration a register configuration a register (address = 0x000) [reset = 0x30] 0x001 undefined reserved reserved 0x002 0x00 device_config device configuration register device configuration register (address = 0x002) [reset = 0x00] 0x003 0x03 chip_type chip type register chip type register (address = 0x003) [reset = 0x03] 0x004-0x005 0x0020 chip_id chip id registers chip id register (address = 0x004 to 0x005) [reset = 0x0020] 0x006 0x0a chip_version chip version register chip version register (address = 0x006) [reset = 0x01] 0x007-0x00b undefined reserved reserved 0x00c-0x00d 0x0451 vendor_id vendor identification register vendor identification register (address = 0x00c to 0x00d) [reset = 0x0451] 0x00e-0x00f undefined reserved reserved 7.6.1.1.1 configuration a register (address = 0x000) [reset = 0x30] figure 89. configuration a register (config_a) 7 6 5 4 3 2 1 0 soft_reset reserved addr_asc sdo_active reserved r/w-0 r-0 r/w-1 r-1 r-0000 table 45. config_a field descriptions bit field type reset description 7 soft_reset r/w 0 setting this bit results in full reset of the device. this bit is self- clearing. after writing this bit, the device may take up to 750 ns to reset. during this time, do not perform any spi transactions. 6 reserved r 0 reserved 5 addr_asc r/w 1 0: descend ? decrement address while streaming reads/writes 1: ascend ? increment address while streaming reads/writes (default) 4 sdo_active r 1 always returns 1 indicating that device always uses 4-wire spi mode 3-0 reserved r 0000 reserved 7.6.1.1.2 device configuration register (address = 0x002) [reset = 0x00] figure 90. device configuration register (device_config) 7 6 5 4 3 2 1 0 reserved mode r-0000 00 r/w-00
85 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 46. device_config field descriptions bit field type reset description 7-2 reserved r 0000 00 reserved 1-0 mode r/w 00 spi 3.0 specification has 1 as low power functional mode, 2 as low power fast resume and 3 as power-down. this chip does not support these modes. 0: normal operation ? full power and full performance (default) 1: normal operation ? full power and full performance 2: power down - everything powered down. only use for brief periods of time to calibrate on-chip temperature diode measurement. please see note beneath recommended operating conditions for more information. 3: power down - everything powered down. only use for brief periods of time to calibrate on-chip temperature diode measurement. please see note beneath recommended operating conditions for more information.
86 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.1.3 chip type register (address = 0x003) [reset = 0x03] figure 91. chip type register (chip_type) 7 6 5 4 3 2 1 0 reserved chip_type r-0000 r-0011 table 47. chip_type field descriptions bit field type reset description 7-4 reserved r 0000 reserved 3-0 chip_type r 0011 always returns 0x3, indicating that the part is a high speed adc. 7.6.1.1.4 chip id register (address = 0x004 to 0x005) [reset = 0x0020] figure 92. chip id register (chip_id) 15 14 13 12 11 10 9 8 chip_id[15:8] r-0x00h 7 6 5 4 3 2 1 0 chip_id[7:0] r-0x20h table 48. chip_id field descriptions bit field type reset description 15-0 chip_id r 0x0020h always returns 0x0020 to indicate that this chip is an adc12dj3200 7.6.1.1.5 chip version register (address = 0x006) [reset = 0x01] figure 93. chip version register (chip_version) 7 6 5 4 3 2 1 0 chip_version r-0000 1010 table 49. chip_version field descriptions bit field type reset description 7-0 chip_version r 0000 1010 chip version, returns 0x0a
87 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.1.6 vendor identification register (address = 0x00c to 0x00d) [reset = 0x0451] figure 94. vendor identification register (vendor_id) 15 14 13 12 11 10 9 8 vendor_id[15:8] r-0x04h 7 6 5 4 3 2 1 0 vendor_id[7:0] r-0x51h table 50. vendor_id field descriptions bit field type reset description 15-0 vendor_id r 0x0451h always returns 0x0451 (ti vendor id) 7.6.1.2 user spi configuration (0x010 to 0x01f) table 51. user spi configuration registers address reset acronym register name section 0x010 0x00 usr0 user spi configuration register user spi configuration register (address = 0x010) [reset = 0x00] 0x011-0x01f undefined reserved reserved 7.6.1.2.1 user spi configuration register (address = 0x010) [reset = 0x00] figure 95. user spi configuration register (usr0) 7 6 5 4 3 2 1 0 reserved addr_hold r-0000 000 r/w-0 table 52. usr0 field descriptions bit field type reset description 7-1 reserved r/w 0000 000 0 addr_hold r/w 0 0: use addr_asc bit to define what happens to address during streaming (default). 1: address stays static throughout streaming operation. useful for reading/writing calibration vector information at cal_data register.
88 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.3 miscellaneous analog registers (0x020 to 0x047) table 53. miscellaneous analog registers address reset acronym register name section 0x020-0x028 undefined reserved reserved 0x029 0x00 clk_ctrl0 clock control register 0 clock control register 0 (address = 0x029) [reset = 0x00] 0x02a 0x20 clk_ctrl1 clock control register 1 clock control register 1 (address = 0x02a) [reset = 0x00] 0x02b undefined reserved reserved 0x02c-0x02e undefined sysref_pos sysref capture position register sysref capture position register (address = 0x02c-0x02e) [reset = undefined] 0x02f undefined reserved reserved 0x030-0x031 0xa000 fs_range_a ina full scale range adjust register ina full scale range adjust register (address = 0x030-0x031) [reset = 0xa000] 0x032-0x033 0xa000 fs_range_b inb full scale range adjust register inb full scale range adjust register (address = 0x032-0x033) [reset = 0xa000] 0x034-0x037 undefined reserved reserved 0x038 0x00 bg_bypass internal reference bypass register internal reference bypass register (address = 0x038) [reset = 0x00] 0x039-0x03a undefined reserved reserved 0x03b 0x00 sync_ctrl tmstp+/- control register tmstp+/- control register (address = 0x03b) [reset = 0x00] 0x03c-0x047 undefined reserved reserved 7.6.1.3.1 clock control register 0 (address = 0x029) [reset = 0x00] figure 96. clock control register 0 (clk_ctrl0) 7 6 5 4 3 2 1 0 reserved sysref_pro c_en sysref_rec v_en sysref_zoo m sysref_sel r/w-0 r/w-0 r/w-0 r/w-0 r/w-0000 table 54. clk_ctrl0 field descriptions bit field type reset description 7 reserved r/w 0 reserved 6 sysref_proc_en r/w 0 enable the sysref processor. this must be set to allow the part to process sysref events. sysref_recv_en must be set before setting sysref_proc_en. 5 sysref_recv_en r/w 0 set this bit to enable the sysref receiver circuit 4 sysref_zoom r/w 0 set this bit to ? zoom ? in the sysref strobe status (impacts sysref_pos) 3-0 sysref_sel r/w 0000 set this field to select which sysref delay to use. set this based on the results returned by sysref_pos. you must set this to 0 to use sysref calibration. 7.6.1.3.2 clock control register 1 (address = 0x02a) [reset = 0x00] figure 97. clock control register 1 (clk_ctrl1) 7 6 5 4 3 2 1 0 reserved devclk_lvpe cl_en sysref_lvpe cl_en sysref_inve rted r/w-0010 0 r/w-0 r/w-0 r/w-0
89 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 55. clk_ctrl1 field descriptions bit field type reset description 7-3 reserved r/w 0010 0 reserved 2 devclk_lvpecl_en r/w 0 activate low voltage pecl mode for devclk 1 sysref_lvpecl_en r/w 0 activate low voltage pecl mode for sysref 0 sysref_inverted r/w 0 inverts the sysref signal used for alignment
90 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.3.3 sysref capture position register (address = 0x02c-0x02e) [reset = undefined] figure 98. sysref capture position register (sysref_pos) 23 22 21 20 19 18 17 16 sysref_pos[23:16] r-undefined 15 14 13 12 11 10 9 8 sysref_pos[15:8] r-undefined 7 6 5 4 3 2 1 0 sysref_pos[7:0] r-undefined table 56. sysref_pos field descriptions bit field type reset description 23-0 sysref_pos r undefined returns a 24-bit status value that indicates the position of the sysref edge with respect to devclk. use this to program sysref_sel. 7.6.1.3.4 ina full scale range adjust register (address = 0x030-0x031) [reset = 0xa000] figure 99. ina full scale range adjust register (fs_range_a) 15 14 13 12 11 10 9 8 fs_range_a[15:8] r/w-0xa0h 7 6 5 4 3 2 1 0 fs_range_a[7:0] r/w-0x00h table 57. fs_range_a field descriptions bit field type reset description 15-0 fs_range_a r/w 0xa000h enables adjustment of the analog full scale range for ina 0x0000: settings below 0x2000 may result in degraded device performance. 0x2000: 500 mvpp - recommended minimum setting. 0xa000: 800 mvpp (default) 0xffff: 1000 mvpp 7.6.1.3.5 inb full scale range adjust register (address = 0x032-0x033) [reset = 0xa000] figure 100. inb full scale range adjust register (fs_range_b) 15 14 13 12 11 10 9 8 fs_range_b[15:8] r/w-0xa0 7 6 5 4 3 2 1 0 fs_range_b[7:0] r/w-0x00
91 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 58. fs_range_b field descriptions bit field type reset description 15-0 fs_range_b r/w 0xa000h enables adjustment of the analog full scale range for inb 0x0000: settings below 0x2000 may result in degraded device performance. 0x2000: 500 mvpp - recommended minimum setting. 0xa000: 800 mvpp (default) 0xffff: 1000 mvpp
92 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.3.6 internal reference bypass register (address = 0x038) [reset = 0x00] figure 101. internal reference bypass register (bg_bypass) 7 6 5 4 3 2 1 0 reserved bg_bypass r/w-0000 000 r/w-0 table 59. bg_bypass field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 bg_bypass r/w 0 when set, va11 is used as the voltage reference instead of the internal reference 7.6.1.3.7 tmstp+/- control register (address = 0x03b) [reset = 0x00] figure 102. tmstp+/- control register (tmstp_ctrl) 7 6 5 4 3 2 1 0 reserved tmstp_lvpe cl_en tmstp_recv _en r/w-0000 00 r/w-0 r/w-0 table 60. tmstp_ctrl field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 tmstp_lvpecl_en r/w 0 when set, activates the low voltage pecl mode for the differential tmstp+/- input 0 tmstp_recv_en r/w 0 enables the differential tmstp+/- input 7.6.1.4 serializer registers (0x048 to 0x05f) table 61. serializer registers address reset acronym register name section 0x048 0x00 ser_pe serializer pre-emphasis control register 0x049-0x05f undefined reserved reserved 7.6.1.4.1 serializer pre-emphasis control register (address = 0x048) [reset = 0x00] figure 103. serializer pre-emphasis control register (ser_pe) 7 6 5 4 3 2 1 0 reserved ser_pe r/w-0000 r/w-0000 table 62. ser_pe field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 ser_pe r/w 0000 sets the pre-emphasis for the serial lanes to compensate for the low-pass response of the pcb trace. this is a global setting that affects all 16 lanes.
93 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5 calibration registers (0x060 to 0x0ff) table 63. calibration registers address reset acronym register name section 0x060 0x01 input_mux input mux control register input mux control register (address = 0x060) [reset = 0x01] 0x061 0x01 cal_en calibration enable register calibration enable register (address = 0x061) [reset = 0x01] 0x062 0x01 cal_cfg0 calibration configuration 0 register calibration configuration 0 register (address = 0x062) [reset = 0x01] 0x063-0x069 undefined reserved reserved 0x06a undefined cal_status calibration status register calibration status register (address = 0x06a) [reset = undefined] 0x06b 0x00 cal_pin_cfg calibration pin configuration register calibration pin configuration register (address = 0x06b) [reset = 0x00] 0x06c 0x01 cal_soft_trig calibration software trigger register calibration software trigger register (address = 0x06c) [reset = 0x01] 0x06d undefined reserved reserved 0x06e 0x88 cal_lp low-power background calibration register low-power background calibration register (address = 0x06e) [reset = 0x88] 0x06f undefined reserved reserved 0x070 0x00 cal_data_en calibration data enable register calibration data enable register (address = 0x070) [reset = 0x00] 0x071 undefined cal_data calibration data register calibration data register (address = 0x071) [reset = undefined] 0x072-0x079 undefined reserved reserved 0x07a undefined gain_trim_a channel a gain trim register channel a gain trim register (address = 0x07a) [reset = undefined] 0x07b undefined gain_trim_b channel b gain trim register channel b gain trim register (address = 0x07b) [reset = undefined] 0x07c undefined bg_trim band-gap reference trim register band-gap reference trim register (address = 0x07c) [reset = undefined] 0x07d undefined reserved reserved 0x07e undefined rtrim_a vina input resistor trim register vina input resistor trim register (address = 0x07e) [reset = undefined] 0x07f undefined rtrim_b vinb input resistor trim register vinb input resistor trim register (address = 0x07f) [reset = undefined] 0x080 undefined tadj_a_fg90 timing adjustment for a-adc, single channel mode, foreground calibration register timing adjust for a-adc, single channel mode, foreground calibration register (address = 0x080) [reset = undefined] 0x081 undefined tadj_b_fg0 timing adjustment for b-adc, single channel mode, foreground calibration register timing adjust for b-adc, single channel mode, foreground calibration register (address = 0x081) [reset = undefined] 0x082 undefined tadj_a_bg90 timing adjustment for a-adc, single channel mode, background calibration register timing adjust for a-adc, single channel mode, background calibration register (address = 0x082) [reset = undefined] 0x083 undefined tadj_c_bg0 timing adjustment for c-adc, single channel mode, background calibration register timing adjust for c-adc, single channel mode, background calibration register (address = 0x084) [reset = undefined] 0x084 undefined tadj_c_bg90 timing adjustment for c-adc, single channel mode, background calibration register timing adjust for c-adc, single channel mode, background calibration register (address = 0x084) [reset = undefined] 0x085 undefined tadj_b_bg0 timing adjustment for b-adc, single channel mode, background calibration register timing adjust for b-adc, single channel mode, background calibration register (address = 0x085) [reset = undefined] 0x086 undefined tadj_a timing adjustment for a-adc, dual channel mode register timing adjust for a-adc, dual channel mode register (address = 0x086) [reset = undefined] 0x087 undefined tadj_ca timing adjustment for c-adc acting for a- adc, dual channel mode register timing adjust for c-adc acting for a- adc, dual channel mode register (address = 0x087) [reset = undefined] 0x088 undefined tadj_cb timing adjustment for c-adc acting for b- adc, dual channel mode register timing adjust for c-adc acting for b- adc, dual channel mode register (address = 0x088) [reset = undefined]
94 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 63. calibration registers (continued) address reset acronym register name section 0x089 undefined tadj_b timing adjustment for b-adc, dual channel mode register timing adjust for b-adc, dual channel mode register (address = 0x089) [reset = undefined] 0x08a-0x08b undefined oadj_a_ina offset adjustment for a-adc and ina register offset adjustment for a-adc and ina register (address = 0x08a-0x08b) [reset = undefined] 0x08c-0x08d undefined oadj_a_inb offset adjustment for a-adc and inb register offset adjustment for a-adc and inb register (address = 0x08c-0x08d) [reset = undefined] 0x08e-0x08f undefined oadj_c_ina offset adjustment for c-adc and ina register offset adjustment for c-adc and ina register (address = 0x08e-0x08f) [reset = undefined] 0x090-0x091 undefined oadj_c_inb offset adjustment for c-adc and inb register offset adjustment for c-adc and inb register (address = 0x090-0x091) [reset = undefined] 0x092-0x093 undefined oadj_b_ina offset adjustment for b-adc and ina register offset adjustment for b-adc and ina register (address = 0x092-0x093) [reset = undefined] 0x094-0x095 undefined oadj_b_inb offset adjustment for b-adc and inb register offset adjustment for b-adc and inb register (address = 0x094-0x095) [reset = undefined] 0x096 undefined reserved reserved 0x097 0x00 0sfilt0 offset filtering control 0 offset filtering control 0 register (address = 0x097) [reset = 0x00] 0x098 0x33 osfilt1 offset filtering control 1 offset filtering control 1 register (address = 0x098) [reset = 0x33] 0x099-0x0ff undefined reserved reserved
95 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.1 input mux control register (address = 0x060) [reset = 0x01] figure 104. input mux control register (input_mux) 7 6 5 4 3 2 1 0 reserved dual_input reserved single_input r/w-000 r/w-0 r/w-00 r/w-01 table 64. input_mux field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 dual_input r/w 0 select inputs for dual channel modes. if jmode is selecting a single channel mode, this register has no effect. 0: a channel samples ina, b channel samples inb (no swap) (default) 1: a channel samples inb, b channel samples ina (swap) 3-2 reserved r/w 00 reserved 1-0 single_input r/w 01 defines which input is sampled in single channel mode. if jmode is not selecting a single channel mode, this register has no effect. 0: reserved 1: ina is used (default) 2: inb is used 3: reserved 7.6.1.5.2 calibration enable register (address = 0x061) [reset = 0x01] figure 105. calibration enable register (cal_en) 7 6 5 4 3 2 1 0 reserved cal_en r/w-0000 000 r/w-1 table 65. cal_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_en r/w 1 calibration enable. set high to run calibration. set low to hold calibration in reset to program new calibration settings. clearing cal_en also resets the clock dividers that clock the digital block and jesd204b interface. some calibration registers require clearing cal_en before making any changes. all registers with this requirement contain a note in their descriptions. after changing the registers, set cal_en to re-run calibration with the new settings. always set cal_en before setting jesd_en. always clear jesd_en before clearing cal_en.
96 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.3 calibration configuration 0 register (address = 0x062) [reset = 0x01] only change this register while cal_en is 0. figure 106. calibration configuration 0 register (cal_cfg0) 7 6 5 4 3 2 1 0 reserved cal_osfilt cal_bgos cal_os cal_bg cal_fg r/w-000 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 table 66. cal_cfg0 field descriptions bit field type reset description 7-5 reserved r/w 0000 reserved 4 cal_osfilt r/w 0 enable offset filtering by setting this bit high. 3 cal_bgos r/w 0 0 : disable background offset calibration (default) 1: enable background offset calibration (requires cal_bg to be set). 2 cal_os r/w 0 0 : disable foreground offset calibration (default) 1: enable foreground offset calibration (requires cal_fg to be set) 1 cal_bg r/w 0 0 : disable background calibration (default) 1: enable background calibration 0 cal_fg r/w 1 0 : reset calibration values, skip foreground calibration 1: reset calibration values, then run foreground calibration (default) 7.6.1.5.4 calibration status register (address = 0x06a) [reset = undefined] figure 107. calibration status register (cal_status) 7 6 5 4 3 2 1 0 reserved cal_stoppe d fg_done r r r table 67. cal_status field descriptions bit field type reset description 7-2 reserved r reserved 1 cal_stopped r this bit will return a 1 when background calibration has successfully stopped at the requested phase. this bit will return a 0 once calibration has started operating again. if background calibration is disabled, this bit will be set once foreground calibration is completed or skipped. 0 fg_done r this bit is set high when foreground calibration has completed
97 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.5 calibration pin configuration register (address = 0x06b) [reset = 0x00] figure 108. calibration pin configuration register (cal_pin_cfg) 7 6 5 4 3 2 1 0 reserved cal_status_sel cal_trig_en r/w-0000 0 r/w-00 r/w-0 table 68. cal_pin_cfg field descriptions bit field type reset description 7-3 reserved r/w 0000 0 reserved 2-1 cal_status_sel r/w 00 0: calstat output pin matches fg_done 1: reserved 2: calstat output pin matches alarm 3: calstat output pin is always low. 0 cal_trig_en r/w 0 choose hardware or software trigger source 0: use the cal_soft_trig register for the calibration trigger. the cal_trig input is disabled (ignored). 1: use the cal_trig input for the calibration trigger. the cal_soft_trig register is ignored. 7.6.1.5.6 calibration software trigger register (address = 0x06c) [reset = 0x01] figure 109. calibration software trigger register (cal_soft_trig) 7 6 5 4 3 2 1 0 reserved cal_soft_tr ig r/w-0000 000 r/w-1 table 69. cal_soft_trig field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_soft_trig r/w 1 cal_soft_trig is a software bit to provide the functionality of the cal_trig input. program cal_trig_en=0 to use cal_soft_trig for the calibration trigger. note: if no calibration trigger is needed, leave cal_trig_en=0 and cal_soft_trig=1 (trigger set high). 7.6.1.5.7 low-power background calibration register (address = 0x06e) [reset = 0x88] figure 110. low-power background calibration register (cal_lp) 7 6 5 4 3 2 1 0 lp_sleep_dly lp_wake_dly reserved lp_trig lp_en r/w-010 r/w-01 r/w-0 r/w-0 r/w-0
98 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 70. cal_lp field descriptions bit field type reset description 7-5 lp_sleep_dly r/w 010 adjust how long an adc sleeps before waking up for calibration (only applys when lp_en=1 and lp_trig=0). values below 4 are not recommended due to limited overall power reduction benefits. 0: sleep delay = (2 3 +1)*256*t devclk 1: sleep delay = (2 15 +1)*256*t devclk 2: sleep delay = (2 18 +1)*256*t devclk 3: sleep delay = (2 21 +1)*256*t devclk 4: sleep delay = (2 24 +1)*256*t devclk : default approximately 1338ms with 3.2 ghz clock. 5: sleep delay = (2 27 +1)*256*t devclk 6: sleep delay = (2 30 +1)*256*t devclk 7: sleep delay = (2 33 +1)*256*t devclk 4-3 lp_wake_dly r/w 01 adjust how much time is given up for settling before calibrating an adc after it wakes up (only applies when lp_en=1). values lower than 1 are not recommended as there will be insufficient time for the core to stabilize before calibration begins. 0:wake delay = (2 3 +1)*256*t devclk 1: wake delay = (2 18 +1)*256*t devclk : default approximately 21ms with 3.2 ghz clock. 2: wake delay = (2 21 +1)*256*t devclk 3: wake delay = (2 24 +1)*256*t devclk 2 reserved r/w 0 reserved 1 lp_trig r/w 0 0: adc sleep duration is set by lp_sleep_dly (autonomous mode). 1: adcs sleep until woken by a trigger. an adc is awoken when the calibration trigger (cal_soft_trig bit or cal_trig input) is low. 0 lp_en r/w 0 0: disable low-power background calibration (default) 1: enable low-power background calibration (only applies when cal_bg=1). 7.6.1.5.8 calibration data enable register (address = 0x070) [reset = 0x00] figure 111. register (cal_data_en) 7 6 5 4 3 2 1 0 reserved cal_data_en r/w-0000 000 r/w-0 table 71. cal_data_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 cal_data_en r/w 0 set this bit to enable the cal_data register to enable reading and writing of calibration data. see calibration data read/write for more information.
99 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.9 calibration data register (address = 0x071) [reset = undefined] figure 112. calibration data register (cal_data) 7 6 5 4 3 2 1 0 cal_data r/w table 72. cal_data field descriptions bit field type reset description 7-0 cal_data r/w undefined after setting cal_data_en, repeated reads of this register will return all the calibration values for the adcs. repeated writes of this register will input all the calibration values for the adcs. to read the calibration data, read the register 673 times. to write the vector, write the register 673 times with previously stored calibration data. to speed up the read/write operation, set addr_hold=1 and use streaming read or write process. important: accessing the cal_data register while cal_stopped=0 will corrupt the calibration. also, stopping the process before reading or writing 673 times will leave the calibration data in an invalid state. 7.6.1.5.10 channel a gain trim register (address = 0x07a) [reset = undefined] figure 113. channel a gain trim register (gain_trim_a) 7 6 5 4 3 2 1 0 gain_trim_a r/w table 73. gain_trim_a field descriptions bit field type reset description 7-0 gain_trim_a r/w undefined this register enables gain trim of channel a. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.11 channel b gain trim register (address = 0x07b) [reset = undefined] figure 114. channel b gain trim register (gain_trim_b) 7 6 5 4 3 2 1 0 gain_trim_b r/w table 74. gain_trim_b field descriptions bit field type reset description 7-0 gain_trim_b r/w undefined this register enables gain trim of channel b. after reset, the factory trimmed value can be read and adjusted as required.
100 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.12 band-gap reference trim register (address = 0x07c) [reset = undefined] figure 115. band-gap reference trim register (bg_trim) 7 6 5 4 3 2 1 0 reserved bg_trim r/w-0000 r/w table 75. bg_trim field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 bg_trim r/w undefined this register enables trim of the internal band-gap reference. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.13 vina input resistor trim register (address = 0x07e) [reset = undefined] figure 116. vina input resistor trim register (rtrim_a) 7 6 5 4 3 2 1 0 rtrim r/w table 76. rtrim_a field descriptions bit field type reset description 7-0 rtrim_a r/w undefined this register controls vina adc input termination trim. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.14 vinb input resistor trim register (address = 0x07f) [reset = undefined] figure 117. vinb input resistor trim register (rtrim_b) 7 6 5 4 3 2 1 0 rtrim r/w table 77. rtrim_b field descriptions bit field type reset description 7-0 rtrim_b r/w undefined this register controls vinb adc input termination trim. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.15 timing adjust for a-adc, single channel mode, foreground calibration register (address = 0x080) [reset = undefined] figure 118. register (tadj_a_fg90) 7 6 5 4 3 2 1 0 tadj_a_fg90 r/w
101 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 78. tadj_a_fg90 field descriptions bit field type reset description 7-0 tadj_a_fg90 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.16 timing adjust for b-adc, single channel mode, foreground calibration register (address = 0x081) [reset = undefined] figure 119. register (tadj_b_fg0) 7 6 5 4 3 2 1 0 tadj_b_fg0 r/w table 79. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_b_fg0 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required.
102 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.17 timing adjust for a-adc, single channel mode, background calibration register (address = 0x082) [reset = undefined] figure 120. register (tadj_a_bg90) 7 6 5 4 3 2 1 0 tadj_a_bg90 r/w table 80. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_a_bg90 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.18 timing adjust for c-adc, single channel mode, background calibration register (address = 0x083) [reset = undefined] figure 121. register (tadj_c_bg0) 7 6 5 4 3 2 1 0 tadj_c_bg0 r/w table 81. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_c_bg0 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.19 timing adjust for c-adc, single channel mode, background calibration register (address = 0x084) [reset = undefined] figure 122. register (tadj_c_bg90) 7 6 5 4 3 2 1 0 tadj_c_bg90 r/w table 82. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_c_bg90 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required.
103 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.20 timing adjust for b-adc, single channel mode, background calibration register (address = 0x085) [reset = undefined] figure 123. register (tadj_b_bg0) 7 6 5 4 3 2 1 0 tadj_b_bg0 r/w table 83. tadj_b_fg0 field descriptions bit field type reset description 7-0 tadj_b_bg0 r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.21 timing adjust for a-adc, dual channel mode register (address = 0x086) [reset = undefined] figure 124. register (tadj_a) 7 6 5 4 3 2 1 0 tadj_a r/w table 84. tadj_a field descriptions bit field type reset description 7-0 tadj_a r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.22 timing adjust for c-adc acting for a-adc, dual channel mode register (address = 0x087) [reset = undefined] figure 125. register (tadj_ca) 7 6 5 4 3 2 1 0 tadj_ca r/w table 85. tadj_ca field descriptions bit field type reset description 7-0 tadj_ca r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required.
104 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.23 timing adjust for c-adc acting for b-adc, dual channel mode register (address = 0x088) [reset = undefined] figure 126. register (tadj_cb) 7 6 5 4 3 2 1 0 tadj_cb r/w table 86. tadj_cb field descriptions bit field type reset description 7-0 tadj_cb r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.24 timing adjust for b-adc, dual channel mode register (address = 0x089) [reset = undefined] figure 127. register (tadj_b) 7 6 5 4 3 2 1 0 tadj_b r/w table 87. tadj_b field descriptions bit field type reset description 7-0 tadj_b r/w undefined this register (and other tadj* registers that follow it) are used to adjust the sampling instant of each adc core. different tadj registers apply to different adcs under different modes or phases of background calibration. after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.5.25 offset adjustment for a-adc and ina register (address = 0x08a-0x08b) [reset = undefined] figure 128. register (oadj_a_ina) 15 14 13 12 11 10 9 8 reserved oadj_a_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_a_ina[7:0] r/w table 88. oadj_a_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_a_ina r/w undefined offset adjustment value for adc0 (a-adc) applied when adc0 samples ina. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1
105 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.26 offset adjustment for a-adc and inb register (address = 0x08c-0x08d) [reset = undefined] figure 129. register (oadj_a_inb) 15 14 13 12 11 10 9 8 reserved oadj_a_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_a_inb[7:0] r/w table 89. oadj_a_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_a_inb r/w undefined offset adjustment value for adc0 (a-adc) applied when adc0 samples inb. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1 7.6.1.5.27 offset adjustment for c-adc and ina register (address = 0x08e-0x08f) [reset = undefined] figure 130. register (oadj_c_ina) 15 14 13 12 11 10 9 8 reserved oadj_c_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_c_ina[7:0] r/w table 90. oadj_c_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_c_ina r/w undefined offset adjustment value for adc1 (a-adc) applied when adc1 samples ina. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1
106 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.28 offset adjustment for c-adc and inb register (address = 0x090-0x091) [reset = undefined] figure 131. register (oadj_c_inb) 15 14 13 12 11 10 9 8 reserved oadj_c_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_c_inb[7:0] r/w table 91. oadj_c_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_c_inb r/w undefined offset adjustment value for adc1 (a-adc) applied when adc1 samples inb. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1 7.6.1.5.29 offset adjustment for b-adc and ina register (address = 0x092-0x093) [reset = undefined] figure 132. register (oadj_b_ina) 15 14 13 12 11 10 9 8 reserved oadj_b_ina[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_b_ina[7:0] r/w table 92. oadj_b_ina field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_b_ina r/w undefined offset adjustment value for adc2 (b-adc) applied when adc2 samples ina. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1
107 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.30 offset adjustment for b-adc and inb register (address = 0x094-0x095) [reset = undefined] figure 133. register (oadj_b_inb) 15 14 13 12 11 10 9 8 reserved oadj_b_inb[11:8] r/w-0000 r/w 7 6 5 4 3 2 1 0 oadj_b_inb[7:0] r/w table 93. oadj_b_inb field descriptions bit field type reset description 15-12 reserved r/w 0000 reserved 11-0 oadj_b_inb r/w undefined offset adjustment value for adc2 (b-adc) applied when adc2 samples inb. the format is unsigned. after reset, the factory trimmed value can be read and adjusted as required. important notes: ? never write oadj* registers while foreground calibration is underway ? never write oadj* registers if cal_bg and cal_bgos are set ? if cal_os=1 and cal_bgos=0, only read oadj* registers if fg_done=1 ? if cal_bg=1 and cal_bgos=1, only read oadj* register if cal_stopped=1
108 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.31 offset filtering control 0 register (address = 0x097) [reset = 0x00] figure 134. register (osfilt0) 7 6 5 4 3 2 1 0 reserved dc_restore r/w-0000 000 r/w table 94. osfilt0 field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 dc_restore r/w 0 when set the offset filtering feature (enabled by cal_osfilt) will filter only the offset mismatch across adc banks and will not remove the frequency content near dc. when cleared, the feature filters all offsets from all banks, thus filtering all dc content in the signal. see offset filtering feature description.
109 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.5.32 offset filtering control 1 register (address = 0x098) [reset = 0x33] figure 135. register (osfilt1) 7 6 5 4 3 2 1 0 osfilt_bw osfilt_soak r/w-0011 r/w-0011 table 95. osfilt1 field descriptions bit field type reset description 7-4 osfilt_bw r/w 0011 this adjusts the iir filter bandwidth for the offset filtering feature (enabled by cal_osfilt). more bandwidth will suppress more flicker noise from the adcs and reduce the offset spurs. less bandwidth will minimize the impact of the filters on the mission mode signal. osfilt_bw: iir coefficient: -3db bandwidth (single sided) 0: reserved: reserved 1: 2 -10 : 609e-9*f devclk 2: 2 -11 : 305e-9*f devclk 3: 2 -12 : 152e-9*f devclk 4: 2 -13 : 76e-9*f devclk 5: 2 -14 : 38e-9*f devclk 6-15: reserved 3-0 osfilt_soak r/w 0011 this adjusts the iir soak time for the offset filtering feature. this applies when offset filtering and background calibration are both enabled. this field determines how long the iir filter is allowed to settle when it is first connected to an adc after the adc is calibrated. after the soak time completes, the adc is placed online using the iir filter. it is recommended to set osfilt_soak = osfilt_bw. 7.6.1.6 adc bank registers (0x100 to 0x15f) table 96. adc bank registers address reset acronym register name section 0x100-0x101 undefined reserved reserved 0x102 undefined b0_time_0 timing adjustment for bank 0 (0 clock) register timing adjustment for bank 0 (0 clock) register (address = 0x102) [reset = undefined] 0x103 undefined b0_time_90 timing adjustment for bank 0 (-90 clock) register timing adjustment for bank 0 (-90 clock) register (address = 0x103) [reset = undefined] 0x104-0x111 undefined reserved reserved 0x112 undefined b1_time_0 timing adjustment for bank 1 (0 clock) register timing adjustment for bank 1 (0 clock) register (address = 0x112) [reset = undefined] 0x113 undefined b1_time_90 timing adjustment for bank 1 (-90 clock) register timing adjustment for bank 1 (-90 clock) register (address = 0x113) [reset = undefined] 0x114-0x121 undefined reserved reserved 0x122 undefined b2_time_0 timing adjustment for bank 2 (0 clock) register timing adjustment for bank 2 (0 clock) register (address = 0x122) [reset = undefined] 0x123 undefined b2_time_90 timing adjustment for bank 2 (-90 clock) register timing adjustment for bank 2 (-90 clock) register (address = 0x123) [reset = undefined] 0x124-0x131 undefined reserved reserved 0x132 undefined b3_time_0 timing adjustment for bank 3 (0 clock) register timing adjustment for bank 3 (0 clock) register (address = 0x132) [reset = undefined] 0x133 undefined b3_time_90 timing adjustment for bank 3 (-90 clock) register timing adjustment for bank 3 (-90 clock) register (address = 0x133) [reset = undefined] 0x134-0x141 undefined reserved reserved
110 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 96. adc bank registers (continued) address reset acronym register name section 0x142 undefined b4_time_0 timing adjustment for bank 4 (0 clock) register timing adjustment for bank 4 (0 clock) register (address = 0x142) [reset = undefined] 0x143 undefined b4_time_90 timing adjustment for bank 4 (-90 clock) register timing adjustment for bank 4 (-90 clock) register (address = 0x143) [reset = undefined] 0x144-0x151 undefined reserved reserved 0x152 undefined b5_time_0 timing adjustment for bank 5 (0 clock) register timing adjustment for bank 5 (0 clock) register (address = 0x152) [reset = undefined] 0x153 undefined b5_time_90 timing adjustment for bank 5 (-90 clock) register timing adjustment for bank 5 (-90 clock) register (address = 0x153) [reset = undefined] 0x154-0x15f undefined reserved reserved
111 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.6.1 timing adjustment for bank 0 (0 clock) register (address = 0x102) [reset = undefined] figure 136. timing adjustment for bank 0 (0 clock) register (b0_time_0) 7 6 5 4 3 2 1 0 b0_time_0 r/w table 97. b0_time_0 field descriptions bit field type reset description 7-0 b0_time_0 r/w undefined time adjustment for bank 0 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.2 timing adjustment for bank 0 (-90 clock) register (address = 0x103) [reset = undefined] figure 137. timing adjustment for bank 0 (-90 clock) register (b0_time_90) 7 6 5 4 3 2 1 0 b0_time_90 r/w table 98. b0_time_90 field descriptions bit field type reset description 7-0 b0_time_90 r/w undefined time adjustment for bank 0 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.3 timing adjustment for bank 1 (0 clock) register (address = 0x112) [reset = undefined] figure 138. timing adjustment for bank 1 (0 clock) register (b1_time_0) 7 6 5 4 3 2 1 0 b1_time_0 r/w table 99. b1_time_0 field descriptions bit field type reset description 7-0 b1_time_0 r/w undefined time adjustment for bank 1 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.4 timing adjustment for bank 1 (-90 clock) register (address = 0x113) [reset = undefined] figure 139. timing adjustment for bank 1 (-90 clock) register (b1_time_90) 7 6 5 4 3 2 1 0 b1_time_90 r/w table 100. b1_time_90 field descriptions bit field type reset description 7-0 b1_time_90 r/w undefined time adjustment for bank 1 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required.
112 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.6.5 timing adjustment for bank 2 (0 clock) register (address = 0x122) [reset = undefined] figure 140. timing adjustment for bank 2 (0 clock) register (b2_time_0) 7 6 5 4 3 2 1 0 b2_time_0 r/w table 101. b2_time_0 field descriptions bit field type reset description 7-0 b2_time_0 r/w undefined time adjustment for bank 2 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.6 timing adjustment for bank 2 (-90 clock) register (address = 0x123) [reset = undefined] figure 141. timing adjustment for bank 2 (-90 clock) register (b2_time_90) 7 6 5 4 3 2 1 0 b2_time_90 r/w table 102. b2_time_90 field descriptions bit field type reset description 7-0 b2_time_90 r/w undefined time adjustment for bank 2 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.7 timing adjustment for bank 3 (0 clock) register (address = 0x132) [reset = undefined] figure 142. timing adjustment for bank 3 (0 clock) register (b3_time_0) 7 6 5 4 3 2 1 0 b3_time_0 r/w table 103. b3_time_0 field descriptions bit field type reset description 7-0 b3_time_0 r/w undefined time adjustment for bank 3 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.8 timing adjustment for bank 3 (-90 clock) register (address = 0x133) [reset = undefined] figure 143. timing adjustment for bank 3 (-90 clock) register (b3_time_90) 7 6 5 4 3 2 1 0 b3_time_90 r/w table 104. b3_time_90 field descriptions bit field type reset description 7-0 b3_time_90 r/w undefined time adjustment for bank 3 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required.
113 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.6.9 timing adjustment for bank 4 (0 clock) register (address = 0x142) [reset = undefined] figure 144. timing adjustment for bank 4 (0 clock) register (b4_time_0) 7 6 5 4 3 2 1 0 b4_time_0 r/w table 105. b4_time_0 field descriptions bit field type reset description 7-0 b4_time_0 r/w undefined time adjustment for bank 4 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.10 timing adjustment for bank 4 (-90 clock) register (address = 0x143) [reset = undefined] figure 145. timing adjustment for bank 4 (-90 clock) register (b4_time_90) 7 6 5 4 3 2 1 0 b4_time_90 r/w table 106. b4_time_90 field descriptions bit field type reset description 7-0 b4_time_90 r/w undefined time adjustment for bank 4 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.11 timing adjustment for bank 5 (0 clock) register (address = 0x152) [reset = undefined] figure 146. timing adjustment for bank 5 (0 clock) register (b5_time_0) 7 6 5 4 3 2 1 0 b5_time_0 r/w table 107. b5_time_0 field descriptions bit field type reset description 7-0 b5_time_0 r/w undefined time adjustment for bank 5 (applied when adc is configured for 0 clock phase). after reset, the factory trimmed value can be read and adjusted as required. 7.6.1.6.12 timing adjustment for bank 5 (-90 clock) register (address = 0x153) [reset = undefined] figure 147. timing adjustment for bank 5 (-90 clock) register (b5_time_90) 7 6 5 4 3 2 1 0 b5_time_90 r/w table 108. b5_time_90 field descriptions bit field type reset description 7-0 b5_time_90 r/w undefined time adjustment for bank 5 (applied when adc is configured for -90 clock phase). after reset, the factory trimmed value can be read and adjusted as required.
114 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.7 lsb control registers (0x160 to 0x1ff) table 109. lsb control registers address reset acronym register name section 0x160 0x00 enc_lsb lsb control bit output register figure 148 0x161-0x1ff undefined reserved reserved 7.6.1.7.1 lsb control bit output register (address = 0x160) [reset = 0x00] figure 148. lsb control bit output register (enc_lsb) 7 6 5 4 3 2 1 0 reserved timestamp_e n r/w-0000 000 r/w-0 table 110. enc_lsb field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 timestamp_en r/w 0 when set, the transport layer transmits the timestamp signal on the lsb of the output samples. only supported in decimate-by-1 (ddc bypass) modes. timestamp_en has priority over cal_state_en. tmstp_recv_en must also be set high when using timestamp. the latency of the timestamp signal (through the entire chip) matches the latency of the analog adc inputs. note 1: in 8-bit modes, the control bit is placed on the lsb of the 8-bit samples (leaving 7-bits of sample data). if the part is configured for 12-bit data, the control bit is placed on the lsb of the 12-bit bit data (leaving 11-bits of sample data). note 2: the control bit that is enabled by this register is never advertised in the ila (the cs field is 0 in the ila). 7.6.1.8 jesd204b registers (0x200 to 0x20f) table 111. jesd204b registers address reset acronym register name section 0x200 0x01 jesd_en jesd204b enable register jesd204b enable register (address = 0x200) [reset = 0x01] 0x201 0x02 jmode jesd204b mode register jesd204b mode register (address = 0x201) [reset = 0x02] 0x202 0x1f km1 jesd204b k parameter register jesd204b k parameter register (address = 0x202) [reset = 0x1f] 0x203 0x01 jsync_n jesd204b manual sync request register jesd204b manual sync request register (address = 0x203) [reset = 0x01] 0x204 0x02 jctrl jesd204b control register jesd204b control register (address = 0x204) [reset = 0x02] 0x205 0x00 jtest jesd204b test pattern control register jesd204b test pattern control register (address = 0x205) [reset = 0x00] 0x206 0x00 did jesd204b did parameter register jesd204b did parameter register (address = 0x206) [reset = 0x00] 0x207 0x00 fchar jesd204b frame character register jesd204b frame character register (address = 0x207) [reset = 0x00] 0x208 undefined jesd_status jesd204b / system status register jesd204b / system status register (address = 0x208) [reset = undefined] 0x209 0x00 pd_ch jesd204b channel power down jesd204b channel power down register (address = 0x209) [reset = 0x00]
115 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 111. jesd204b registers (continued) address reset acronym register name section 0x20a 0x00 jextra_a jesd204b extra lane enable (link a) jesd204b extra lane enable (link a) register (address = 0x20a) [reset = 0x00] 0x20b 0x00 jextra_b jesd204b extra lane enable (link b) jesd204b extra lane enable (link b) register (address = 0x20b) [reset = 0x00] 0x20c-0x20f undefined reserved reserved
116 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.1 jesd204b enable register (address = 0x200) [reset = 0x01] figure 149. jesd204b enable register (jesd_en) 7 6 5 4 3 2 1 0 reserved jesd_en r/w-0000 000 r/w-1 table 112. jesd_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 jesd_en r/w 1 0 : disable jesd204b interface 1 : enable jesd204b interface note 1: before altering other jesd204b registers, you must clear jesd_en. when jesd_en is 0, the block is held in reset and the serializers are powered down. the clocks are gated off to save power. the lmfc counter is also held in reset, so sysref will not align the lmfc. note 2: always set cal_en before setting jesd_en note 3: always clear jesd_en before clearing cal_en 7.6.1.8.2 jesd204b mode register (address = 0x201) [reset = 0x02] figure 150. jesd204b mode register (jmode) 7 6 5 4 3 2 1 0 reserved jmode r/w-000 r/w-0001 0 table 113. jmode field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4-0 jmode r/w 0001 0 specify the jesd204b output mode (including ddc decimation factor) note: this register should only be changed when jesd_en=0 and cal_en=0 7.6.1.8.3 jesd204b k parameter register (address = 0x202) [reset = 0x1f] figure 151. jesd204b k parameter register (km1) 7 6 5 4 3 2 1 0 reserved km1 r/w-000 r/w-1111 1 table 114. km1 field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4-0 km1 r/w 1111 1 k is the number of frames per multiframe and this register must be programmed as k-1. depending on the jmode setting, there are constraints on the legal values of k. (default: km1=31, k=32) note: this register should only be changed when jesd_en is 0.
117 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.4 jesd204b manual sync request register (address = 0x203) [reset = 0x01] figure 152. jesd204b manual sync request register (jsync_n) 7 6 5 4 3 2 1 0 reserved jsync_n r/w-0000 000 r/w-1 table 115. jsync_n field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 jsync_n r/w 1 set this bit to 0 to request jesd204b synchronization (equivalent to the syncse pin being asserted). for normal operation, leave this bit set to 1. note: the jsync_n register can always generate a synchronization request, regardless of the sync_sel register. however, if the selected sync pin is stuck low, you cannot de- assert the synchronization request unless you program sync_sel=2. 7.6.1.8.5 jesd204b control register (address = 0x204) [reset = 0x02] figure 153. jesd204b control register (jctrl) 7 6 5 4 3 2 1 0 reserved sync_sel sformat scr r/w-0000 r/w-00 r/w-1 r/w-0 table 116. jctrl field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-2 sync_sel r/w 00 0: use the syncse input for sync~ function (default) 1: use the tmstp+/- differential input for sync~ function. tmstp_recv_en must also be set. 2: do not use any sync input signal (use software sync~ through jsync_n) 1 sformat r/w 1 output sample format for jesd204b samples 0: offset binary 1: signed 2 ? s complement (default) 0 scr r/w 0 0: scrambler disabled (default) 1: scrambler enabled note: this register should only be changed when jesd_en is 0.
118 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.6 jesd204b test pattern control register (address = 0x205) [reset = 0x00] figure 154. jesd204b test pattern control register (jtest) 7 6 5 4 3 2 1 0 reserved jtest r/w-0000 r/w-0000 table 117. jtest field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-0 jtest r/w 0000 0: test mode disabled. normal operation (default) 1: prbs7 test mode 2: prbs15 test mode 3: prbs23 test mode 4: ramp test mode 5: transport layer test mode 6: d21.5 test mode 7: k28.5 test mode 8: repeated ila test mode 9: modified rpat test mode 10: serial outputs held low 11: serial outputs held high 12 thru 15: reserved note: this register should only be changed when jesd_en is 0. 7.6.1.8.7 jesd204b did parameter register (address = 0x206) [reset = 0x00] figure 155. jesd204b did parameter register (did) 7 6 5 4 3 2 1 0 did r/w-0000 0000 table 118. did field descriptions bit field type reset description 7-0 did r/w 0000 0000 specifies the did (device id) value that is transmitted during the second multiframe of the jesd204b ila. link a will transmit did, and link b will transmit did+1. bit 0 is ignored and always returns 0 (if you program an odd number, it will be decremented to an even number). note: this register should only be changed when jesd_en is 0.
119 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.8 jesd204b frame character register (address = 0x207) [reset = 0x00] figure 156. jesd204b frame character register (fchar) 7 6 5 4 3 2 1 0 reserved fchar r/w-0000 00 r/w-00 table 119. fchar field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1-0 fchar r/w 00 specify which comma character is used to denote end-of-frame. this character is transmitted opportunistically (see section 12.8.5) 0: use k28.7 (default) (jesd204b compliant) 1: use k28.1 (not jesd204b compliant) 2: use k28.5 (not jesd204b compliant) 3: reserved when using a jesd204b receiver, always use fchar=0. when using a general purpose 8b/10b receiver, the k28.7 character may cause issues. when k28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers will re-align to the false comma. to avoid this, program fchar to 1 or 2. note: this register should only be changed when jesd_en is 0. 7.6.1.8.9 jesd204b / system status register (address = 0x208) [reset = undefined] figure 157. jesd204b / system status register (jesd_status) 7 6 5 4 3 2 1 0 reserved link_up sync_statu s realigned aligned pll_locked reserved r r r r/w r/w r r table 120. jesd_status field descriptions bit field type reset description 7 reserved r undefined reserved 6 link_up r undefined when set, indicates that the jesd204b link is up 5 sync_status r undefined returns the state of the jesd204b sync~ signal. 0: sync~ asserted 1: sync~ de-asserted 4 realigned r/w undefined when high, indicates that an internal digital clock, frame clock, or multiframe (lmfc) clock phase was realigned by sysref. writing a 1 to this bit will clear it. 3 aligned r/w undefined when high, indicates that the multiframe (lmfc) clock phase has been established by sysref. the first sysref event after enabling the jesd204b encoder will set this bit. writing a 1 to this bit will clear it. 2 pll_locked r undefined when high, indicates that the pll is locked 1-0 reserved r undefined reserved
120 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.10 jesd204b channel power down register (address = 0x209) [reset = 0x00] figure 158. jesd204b channel power down register (pd_ch) 7 6 5 4 3 2 1 0 reserved pd_bch pd_ach r/w-0000 00 r/w-0 r/w-0 table 121. pd_ch field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 pd_bch r/w 0 when set, the ? b ? adc channel is powered down. the digital channels that are bound to the ? b ? adc channel are also powered down (see dig_bind). important notes: 1. you must set jesd_en=0 before changing pd_ch 2. to power down both adc channels, use mode 3. if both channels are powered down, then the entire jesd204b subsystem (including the pll and lmfc) are powered down 4. if the selected jesd204b mode transmits a and b data on link a, and the b digital channel is disabled, link a remains operational, but the b-channel samples are undefined. 0 pd_ach r/w 0 when set, the ? a ? adc channel is powered down. the digital channels that are bound to the ? a ? adc channel are also powered down (see dig_bind). important notes: 1. you must set jesd_en=0 before changing pd_ch 2. to power down both adc channels, use mode 3. if both channels are powered down, then the entire jesd204b subsystem (including the pll and lmfc) are powered down 4. if the selected jesd204b mode transmits a and b data on link a, and the b digital channel is disabled, link a remains operational, but the b-channel samples are undefined.
121 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.11 jesd204b extra lane enable (link a) register (address = 0x20a) [reset = 0x00] figure 159. jesd204b extra lane enable (link a) register (jextra_a) 7 6 5 4 3 2 1 0 extra_lane_a extra_ser_ a r/w-0000 000 r/w-0 table 122. jesd204b extra lane enable (link a) field descriptions bit field type reset description 7-1 extra_lane_a r/w 0000 000 program these register bits to enable extra lanes (even if the selected jmode does not require the lanes to be enabled). extra_lane_a(n) enables an (n=1 to 7). this register enables the link layer clocks for the affected lanes. to also enable the extra serializes set extra_ser_a=1. 0 extra_ser_a r/w 0 0: only the link layer clocks for extra lanes are enabled. 1: serializers for extra lanes are also enabled. use this mode to transmit data from the extra lanes. important notes: this register should only be changed when jesd_en=0. the bit-rate and mode of the extra lanes are set by the jmode and jtest parameters. this register does not override the pd_ch register, so ensure that the link is enabled to use this feature. to enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.
122 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8.12 jesd204b extra lane enable (link b) register (address = 0x20b) [reset = 0x00] figure 160. jesd204b extra lane enable (link b) register (jextra_b) 7 6 5 4 3 2 1 0 extra_lane_b extra_ser_ b r/w-0000 000 r/w-0 table 123. jesd204b extra lane enable (link b) field descriptions bit field type reset description 7-1 extra_lane_b r/w 0000 000 program these register bits to enable extra lanes (even if the selected jmode does not require the lanes to be enabled). extra_lane_b(n) enables bn (n=1 to 7). this register enables the link layer clocks for the affected lanes. to also enable the extra serializes set extra_ser_b=1. 0 extra_ser_b r/w 0 0: only the link layer clocks for extra lanes are enabled. 1: serializers for extra lanes are also enabled. use this mode to transmit data from the extra lanes. important notes: this register should only be changed when jesd_en=0. the bit-rate and mode of the extra lanes are set by the jmode and jtest parameters. this register does not override the pd_ch register, so ensure that the link is enabled to use this feature. to enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.
123 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9 digital down converter registers (0x210-0x2af) table 124. digital down converter and over-range registers address reset acronym register name section 0x210 0x00 ddc_cfg ddc configuration register ddc configuration register (address = 0x210) [reset = 0x00] 0x211 0xf2 ovr_t0 over-range threshold 0 register over-range threshold 0 register (address = 0x211) [reset = 0xf2] 0x212 0xab ovr_t1 over-range threshold 1 register over-range threshold 1 register (address = 0x212) [reset = 0xab] 0x213 0x07 ovr_cfg over-range configuration register over-range configuration register (address = 0x213) [reset = 0x07] 0x214 0x00 cmode ddc configuration preset mode register ddc configuration preset mode register (address = 0x214) [reset = 0x00] 0x215 0x00 csel ddc configuration preset select register ddc configuration preset select register (address = 0x215) [reset = 0x00] 0x216 0x02 dig_bind digital channel binding register digital channel binding register (address = 0x216) [reset = 0x02] 0x217-0x218 0x0000 nco_rdiv rational nco reference divisor register rational nco reference divisor register (address = 0x217 to 0x218) [reset = 0x0000] 0x219 0x02 nco_sync nco synchronization register nco synchronization register (address = 0x219) [reset = 0x02] 0x21a-0x21f undefined reserved reserved 0x220-0x223 0xc0000000 freqa0 nco frequency (ddc a preset 0) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x224-0x225 0x0000 phasea0 nco phase (ddc a preset 0) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x226-0x227 undefined reserved reserved 0x228-0x22b 0xc0000000 freqa1 nco frequency (ddc a preset 1) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x22c-0x22d 0x0000 phasea1 nco phase (ddc a preset 1) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x22e-0x22f undefined reserved reserved 0x230-0x233 0xc0000000 freqa2 nco frequency (ddc a preset 2) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x234-0x235 0x0000 phasea2 nco phase (ddc a preset 2) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x236-0x237 undefined reserved reserved 0x238-0x23b 0xc0000000 freqa3 nco frequency (ddc a preset 3) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x23c-0x23d 0x0000 phasea3 nco phase (ddc a preset 3) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x23e-0x23f undefined reserved reserved 0x240-0x243 0xc0000000 freqb0 nco frequency (ddc b preset 0) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x244-0x245 0x0000 phaseb0 nco phase (ddc b preset 0) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x246-0x247 undefined reserved reserved 0x248-0x24b 0xc0000000 freqb1 nco frequency (ddc b preset 1) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ]
124 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated table 124. digital down converter and over-range registers (continued) address reset acronym register name section 0x24c-0x24d 0x0000 phaseb1 nco phase (ddc b preset 1) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x24e-0x24f undefined reserved reserved 0x250-0x253 0xc0000000 freqb2 nco frequency (ddc b preset 2) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x254-0x255 0x0000 phaseb2 nco phase (ddc b preset 2) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x256-0x257 undefined reserved reserved 0x258-0x25b 0xc0000000 freqb3 nco frequency (ddc b preset 3) nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x25c-0x25d 0x0000 phaseb3 nco phase (ddc b preset 3) nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] 0x25e-0x296 undefined reserved reserved 0x297 undefined spin_id spin identification value spin identification register (address = 0x297) [reset = undefined] 0x298-0x2af undefined reserved reserved
125 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.1 ddc configuration register (address = 0x210) [reset = 0x00] figure 161. ddc configuration register (ddc_cfg) 7 6 5 4 3 2 1 0 reserved d4_ap87 d2_high_pas s invert_spec trum boost r/w-0000 r/w-0 r/w-0 r/w-0 r/w-0 table 125. ddc_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3 d4_ap87 r/w 0 0: decimate-by-4 mode uses 80% alias protection, > 80db suppression 1: decimate-by-4 mode uses 87.5% alias protection, > 60db suppression 2 d2_high_pass r/w 0 0: decimate-by-2 mode uses a low-pass filter 1: decimate-by-2 mode uses a high-pass filter. decimating the high-pass signal will cause spectral inversion. this can be undone by setting invert_spectrum. 1 invert_spectrum r/w 0 0: no inversion applied to output spectrum 1: output spectrum is inverted this register only applies when the ddc is enabled and is producing a real output (not complex). the spectrum is inverted by mixing the signal with fsout/2 (i.e. invert all odd samples). 0 boost r/w 0 ddc gain control. only applies to ddc modes with complex decimation. 0: final filter has 0db gain (default) 1: final filter has 6.02db gain. only use this when you are certain the negative image of your input signal is filtered out by the ddc, otherwise digital clipping may occur. 7.6.1.9.2 over-range threshold 0 register (address = 0x211) [reset = 0xf2] figure 162. over-range threshold 0 register (ovr_t0) 7 6 5 4 3 2 1 0 ovr_t0 r/w-1111 0010 table 126. ovr_t0 field descriptions bit field type reset description 7-0 ovr_t0 r/w 1111 0010 over-range threshold 0. this parameter defines the absolute sample level that causes control bit 0 to be set. the detection level in dbfs (peak) is 20 log10 (ovr_t0 / 256) default: 0xf2 = 242 ? 0.5 dbfs
126 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.3 over-range threshold 1 register (address = 0x212) [reset = 0xab] figure 163. over-range threshold 1 register (ovr_t1) 7 6 5 4 3 2 1 0 ovr_t1 r/w-1010 1011 table 127. ovr_t1 field descriptions bit field type reset description 7-0 ovr_t1 r/w 1010 1011 over-range threshold 1. this parameter defines the absolute sample level that causes control bit 1 to be set. the detection level in dbfs (peak) is 20 log10 (ovr_t1 / 256) default: 0xab = 171 ? 3.5 dbfs 7.6.1.9.4 over-range configuration register (address = 0x213) [reset = 0x07] figure 164. over-range configuration register (ovr_cfg) 7 6 5 4 3 2 1 0 reserved ovr_en ovr_n r/w-0000 r/w-0 r/w-111 (1) changing the ovr_n setting while jesd_en=1 may cause the phase of the monitoring period to change. table 128. ovr_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 0 reserved 3 ovr_en r/w 0 enables over-range status output pins when set high. the ora0, ora1, orb0 and orb1 outputs are held low when ovr_en is set low. this register only effects the over-range output pins (orxx) and not the over-range status embedded in the data samples. 2-0 ovr_n (1) r/w 111 program this register to adjust the pulse extension for the ora0/1 and orb0/1 outputs. the minimum pulse duration of the over-range outputs is 8 * 2 ovr_n devclk cycles. incrementing this field doubles the monitoring period.
127 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.5 ddc configuration preset mode register (address = 0x214) [reset = 0x00] figure 165. ddc configuration preset mode register (cmode) 7 6 5 4 3 2 1 0 reserved cmode r/w-0000 00 r/w-00 table 129. cmode field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1-0 cmode r/w 00 the nco frequency and phase for ddc a are set by the freqax and phaseax registers and the nco frequency and phase for ddc b are set by the freqbx and phasebx registers, where x is the configuration preset (0 through 3). 0: use csel register to select the active nco configuration preset for ddc a and ddc b 1: use ncoa[1:0] pins to select the active nco configuration preset for ddc a and use ncob[1:0] pins to select the active nco configuration preset for ddc b 2: use ncoa[1:0] pins to select the active nco configuration preset for both ddc a and ddc b 3: reserved
128 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.6 ddc configuration preset select register (address = 0x215) [reset = 0x00] figure 166. ddc configuration preset select register (csel) 7 6 5 4 3 2 1 0 reserved cselb csela r/w-0000 r/w-00 r/w-00 table 130. csel field descriptions bit field type reset description 7-4 reserved r/w 0000 reserved 3-2 cselb r/w 00 when cmode=0, this register is used to select the active nco configuration preset for ddc b 1-0 csela r/w 00 when cmode=0, this register is used to select the active nco configuration preset for ddc a example: if csela=0, then freqa0 and phasea0 are the active settings. if csela=1, then freqa1 and phasea1 are the active settings. 7.6.1.9.7 digital channel binding register (address = 0x216) [reset = 0x02] figure 167. digital channel binding register (dig_bind) 7 6 5 4 3 2 1 0 reserved dig_bind_b dig_bind_a r/w-0000 00 r/w-1 r/w-0 table 131. dig_bind field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 dig_bind_b r/w 0 digital channel b input select: 0: digital channel b receives data from adc channel a 1: digital channel b receives data from adc channel b (default) 0 dig_bind_a r/w 0 digital channel a input select: 0: digital channel a receives data from adc channel a (default) 1: digital channel a receives data from adc channel b note 1: when using single channel mode, you must always use the default setting for dig_bind or the part will not work. note 2: you must set jesd_en=0 and cal_en=0 before changing dig_bind. note 3: the dig_bind setting is combined with pd_ach/pd_bch to determine if a digital channel is powered down. each digital channel (and link) is powered down when the adc channel it is bound to is powered down (by pd_ach/pd_bch).
129 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.8 rational nco reference divisor register (address = 0x217 to 0x218) [reset = 0x0000] figure 168. rational nco reference divisor register (nco_rdiv) 15 14 13 12 11 10 9 8 nco_rdiv[15:8] r/w-0000 0000 7 6 5 4 3 2 1 0 nco_rdiv[7:0] r/w-0000 0000 table 132. nco_rdiv field descriptions bit field type reset description 15-0 nco_rdiv r/w 0x0000h sometimes the 32-bit nco frequency word does not provide the desired frequency step size and can only approximate the desired frequency. this results in a frequency error. use this register to eliminate the frequency error. this register is used for all configuration presets. see . 7.6.1.9.9 nco synchronization register (address = 0x219) [reset = 0x02] figure 169. nco synchronization register (nco_sync) 7 6 5 4 3 2 1 0 reserved nco_sync_il a nco_sync_n ext r/w-0000 00 r/w-1 r/w-0 table 133. nco_sync field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 nco_sync_ila r/w 0 when this bit is set, the nco phase is initialized by the lmfc edge that starts the ila sequence (default) 0 nco_sync_next r/w 0 after writing ? 0 ? and then ? 1 ? to this bit, the next sysref rising edge will initialize the nco phase. once the nco phase has been initialized by sysref, the nco will not re-initialize on future sysref edges unless ? 0 ? and ? 1 ? is written to this bit again. use this to align the nco in multiple parts: ? ensure the part is powered up, jesd_en is set, and the device clock is running. ? ensure that sysref is disabled (not toggling). ? program nco_sync_ila=0 on all parts. ? write nco_sync_next=0 on all parts. ? write nco_sync_next=1 on all parts. nco sync is armed. ? instruct the sysref source to generate 1 or more sysref pulses. ? all parts will initialize their nco using the first sysref rising edge.
130 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.9.10 nco frequency (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] figure 170. nco frequency (ddc a or ddc b and preset x) register (freqax or freqbx) 31 30 29 28 27 26 25 24 freqax[31:24] or freqbx[31:24] r/w-0xc0 23 22 21 20 19 18 17 16 freqax[23:16] or freqbx[23:16] r/w-0x00 15 14 13 12 11 10 9 8 freqax[15:8] or freqbx[15:8] r/w-0x00 7 6 5 4 3 2 1 0 freqax[7:0] or freqbx[7:0] r/w-0x00 table 134. freqax or freqbx field descriptions bit field type reset description 31-0 freqax or freqbx r/w see table 124 changing this register after the jesd204b interface is running results in non-deterministic nco phase. if deterministic phase is required, the jesd204b interface must be re-initialized after changing this register. this register can be interpreted as signed or unsigned. see . 7.6.1.9.11 nco phase (ddc a or ddc b and preset x) register (address = see table 124 ) [reset = see table 124 ] figure 171. nco phase (ddc a or ddc b and preset x) register (phaseax or phasebx) 15 14 13 12 11 10 9 8 phaseax[15:8] or phasebx[15:8] r/w-0x00 7 6 5 4 3 2 1 0 phaseax[7:0] or phasebx[7:0] r/w-0x00 table 135. phaseax or phasebx field descriptions bit field type reset description 15-0 phaseax or phasebx r/w see table 124 this value is msb-justified into a 32 ? bit field and then added to the phase accumulator. this register can be interpreted as signed or unsigned. see nco phase offset setting .
131 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.10 spin identification register (address = 0x297) [reset = undefined] figure 172. spin identification register (spin_id) 7 6 5 4 3 2 1 0 reserved spin_id r-000 r table 136. spin_id field descriptions bit field type reset description 7-5 reserved r 000 reserved 4-0 spin_id r see description spin identification value: 0 : adc12dj3200 7.6.2 sysref calibration registers (0x2b0 to 0x2bf) table 137. sysref calibration registers address reset acronym register name section 0x2b0 0x00 src_en sysref calibration enable register sysref calibration enable register (address = 0x2b0) [reset = 0x00] 0x2b1 0x05 src_cfg sysref calibration configuration register sysref calibration configuration register (address = 0x2b1) [reset = 0x05] 0x2b2-0x2b4 undefined src_status sysref calibration status sysref calibration status register (address = 0x2b2 to 0x2b4) [reset = undefined] 0x2b5-0x2b7 0x00 tad devclk aperture delay adjustment register devclk aperture delay adjustment register (address = 0x2b5 to 0x2b7) [reset = 0x000000] 0x2b8 0x00 tad_ramp devclk timing adjust ramp control register devclk timing adjust ramp control register (address = 0x2b8) [reset = 0x00] 0x2b9-0x2bf undefined reserved reserved 7.6.2.1 sysref calibration enable register (address = 0x2b0) [reset = 0x00] figure 173. sysref calibration enable register (src_en) 7 6 5 4 3 2 1 0 reserved src_en r/w-0000 000 r/w-0 table 138. src_en field descriptions bit field type reset description 7-1 reserved r/w 0000 000 reserved 0 src_en r/w 0 0: sysref calibration disabled. use the tad register to manually control the tad[16:0] output and adjust the devclk delay. (default) 1: sysref calibration enabled. the devclk delay is automatically calibrated. the tad register is ignored. a 0-to-1 transition on src_en starts the sysref calibration sequence. program src_cfg before setting src_en. ensure that adc calibration is not currently running before setting src_en.
132 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.2.2 sysref calibration configuration register (address = 0x2b1) [reset = 0x05] figure 174. sysref calibration configuration register (src_cfg) 7 6 5 4 3 2 1 0 reserved src_avg src_hdur r/w-0000 r/w-01 r/w-01 table 139. src_cfg field descriptions bit field type reset description 7-4 reserved r/w 0000 00 reserved 3-2 src_avg r/w 01 specifies the amount of averaging used for sysref calibration. larger values will increase calibration time and reduce the variance of the calibrated value. 0: 4 averages 1: 16 averages 2: 64 averages 3: 256 averages 1-0 src_hdur r/w 01 specifies the duration of each high-speed accumulation for sysref calibration. if the sysref period exceeds the supported value, calibration will fail. larger values will increase calibration time and support longer sysref periods. for a given sysref period, larger values will also reduce the variance of the calibrated value. 0: 4 cycles per accumulation, max sysref period of 85 devclk cycles 1: 16 cycles per accumulation, max sysref period of 1100 devclk cycles 2: 64 cycles per accumulation, max sysref period of 5200 devclk cycles 3: 256 cycles per accumulation, max sysref period of 21580 devclk cycles max duration of sysref calibration is bounded by: t sysrefcal (in devclk cycles) = 256 * 19 * 4 (src_avg + src_hdur + 2)
133 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.2.3 sysref calibration status register (address = 0x2b2 to 0x2b4) [reset = undefined] figure 175. sysref calibration status register (src_status) 23 22 21 20 19 18 17 16 reserved src_done src_tad[16] r r r 15 14 13 12 11 10 9 8 src_tad[15:8] r 7 6 5 4 3 2 1 0 src_tad[7:0] r table 140. src_status field descriptions bit field type reset description 23-18 reserved r undefined reserved 17 src_done r undefined this bit returns ? 1 ? when src_en=1 and sysref calibration has been completed 16-0 src_tad r undefined this field returns the value for tad[16:0] computed by sysref calibration. it is only valid if src_done=1. 7.6.2.4 devclk aperture delay adjustment register (address = 0x2b5 to 0x2b7) [reset = 0x000000] figure 176. devclk aperture delay adjustment register (tad) 23 22 21 20 19 18 17 16 reserved tad_inv r/w-0000 000 r/w-0 15 14 13 12 11 10 9 8 tad_coarse r/w-0000 0000 7 6 5 4 3 2 1 0 tad_fine r/w-0000 0000 table 141. tad field descriptions bit field type reset description 23-17 reserved r/w 0000 000 reserved 16 tad_inv r/w 0 invert devclk by setting this bit equal to 1 15-8 tad_coarse r/w 0000 0000 this register controls the devclk aperture delay adjustment when src_en=0. use this register to manually control the devclk aperture delay when sysref calibration is disabled. if adc calibration or jesd204b is running, it is recommended that you gradually increase or decrease this value (1 code at a time) to avoid clock glitches. refer to switching characteristics for tad_coarse resolution. 7-0 tad_fine r/w 0000 0000 refer to switching characteristics for tad_fine resolution. 7.6.2.5 devclk timing adjust ramp control register (address = 0x2b8) [reset = 0x00]
134 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 177. devclk timing adjust ramp control register (tad_ramp) 7 6 5 4 3 2 1 0 reserved tad_ramp_r ate tad_ramp_e n r/w-0000 00 r/w-0 r/w-0 table 142. tad_ramp field descriptions bit field type reset description 7-2 reserved r/w 0000 00 reserved 1 tad_ramp_rate r/w 0 specifies the ramp rate for the tad[15:8] output when the tad[15:8] register is written while tad_ramp_en=1. 0: tad[15:8] ramps up or down one code per 256 devclk cycles. 1: tad[15:8] ramps up or down 4 codes per 256 devclk cycles. 0 tad_ramp_en r/w 0 tad ramp enable. set this bit if you want the coarse tad adjustments to ramp up or down instead of changing abruptly. 0: after writing the tad[15:8] register the tad[15:7] output port is updated within 1024 devclk cycles. 1: after writing the tad[15:8] register the tad[15:7] output port ramps up or down until it matches the tad[15:8] register.
135 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.3 alarm registers (0x2c0 to 0x2c2) table 143. alarm registers address reset acronym register name section 0x2c0 undefined alarm alarm interrupt status register alarm interrupt register (address = 0x2c0) [reset = undefined] 0x2c1 0x1f alm_status alarm status register alarm status register (address = 0x2c1) [reset = 0x1f] 0x2c2 0x1f alm_mask alarm mask register alarm mask register (address = 0x2c2) [reset = 0x1f] 7.6.3.1 alarm interrupt register (address = 0x2c0) [reset = undefined] figure 178. alarm interrupt register (alarm) 7 6 5 4 3 2 1 0 reserved alarm r r table 144. alarm field descriptions bit field type reset description 7-1 reserved r undefined reserved 0 alarm r undefined this bit returns a ? 1 ? whenever any alarm occurs that is unmasked in the alm_status register. use alm_mask to mask (disable) individual alarms. cal_status_sel can be used to drive the alarm bit onto the calstat output pin to provide a hardware alarm interrupt signal. 7.6.3.2 alarm status register (address = 0x2c1) [reset = 0x1f] figure 179. alarm status register (alm_status) 7 6 5 4 3 2 1 0 reserved pll_alm link_alm realigned_a lm nco_alm clk_alm r/w-000 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 table 145. alm_status field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 pll_alm r/w 1 pll lock lost alarm: this bit is set whenever the pll is not locked. write a ? 1 ? to clear this bit. 3 link_alm r/w 1 link alarm: this bit is set whenever the jesd204b link is enabled, but is not in the data_enc state. write a ? 1 ? to clear this bit. 2 realigned_alm r/w 1 realigned alarm: this bit is set whenever sysref causes the internal clocks (including the lmfc) to be realigned. write a ? 1 ? to clear this bit. 1 nco_alm r/w 1 nco alarm: this bit can be used to detect an upset to the nco phase. this bit is set when any of the following occur: ? the ncos are disabled (jesd_en=0) ? the ncos are synchronized (intentionally or unintentionally) ? any phase accumulators in channel a do not match channel b write a ? 1 ? to clear this bit. 0 clk_alm r/w 1 clock alarm: this bit can be used to detect an upset to the digital block and jesd204b clocks. this bit is set whenever the internal clock dividers for the a and b channels do not match. write a ? 1 ? to clear this bit.
136 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.3.3 alarm mask register (address = 0x2c2) [reset = 0x1f] figure 180. alarm mask register (alm_mask) 7 6 5 4 3 2 1 0 reserved mask_pll_al m mask_link_a lm mask_realig ned_alm mask_nco_a lm mask_clk_al m r/w-000 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 table 146. alm_mask field descriptions bit field type reset description 7-5 reserved r/w 000 reserved 4 mask_pll_alm r/w 1 when set, pll_alm is masked and will not impact the alarm register bit 3 mask_link_alm r/w 1 when set, link_alm is masked and will not impact the alarm register bit 2 mask_realigned_alm r/w 1 when set, realigned_alm is masked and will not impact the alarm register bit 1 mask_nco_alm r/w 1 when set, nco_alm is masked and will not impact the alarm register bit 0 mask_clk_alm r/w 1 when set, clk_alm is masked and will not impact the alarm register bit
137 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) see third-party products disclaimer 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.2 typical application figure 181. typical configuration for wideband rf sampling 8.2.1 design requirements 8.2.1.1 input signal path appropriate band limiting filters should be utilized to reject unwanted frequencies in the input signal path. a 1:2 balun transformer is needed to convert the 50- single-ended signal to 100- differential for input to the adc. the balun outputs can be either ac-coupled, or directly connected to the adc differential inputs, which are terminated internally to gnd. drivers should be selected to provide any needed signal gain, and which have the necessary bandwidth capabilities. baluns should be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have acceptable gain and phase balance over the frequency range of interest. the table below lists a number of recommended baluns for different frequency ranges. table 147. recommended baluns part number manufacturer (1) minimum frequency (mhz) maximum frequency (mhz) bal-0009smg marki microwave 0.5 9000 bal-0208smg marki microwave 2000 8000 tcm2-43x+ mini-circuits 10 4000 tcm2-33wx+ mini-circuits 10 3000 adc adc adc and jesd204b clocking user control logic spi device clk sysref sync~ vina vinb fpga 1 to 16 lanes jesd204b jesd 204b ddc ddc jesd 204b 1:2 balun transformers
138 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) table 147. recommended baluns (continued) part number manufacturer (1) minimum frequency (mhz) maximum frequency (mhz) b0430j50100ahf anaren 400 3000 8.2.1.2 clocking the adc12dj3200clock inputs must be ac-coupled to the device to ensure rated performance. the clock source must have extremely low jitter (integrated phase-noise) to enable rated performance. recommended clock synthesizers include the following: ? lmx2594 ? lmx2592 ? lmx2582 the jesd204b data converter system (adc plus fpga) will require additional sysref and device clocks. the following devices are suitable to generate these clocks. depending on the adc clock frequency and jitter requirements, this device may also be usable as the system clock synthesizer: ? lmk04828 ? lmk04826 ? lmk04821 8.2.2 detailed design procedure certain component values used in conjunction with the adc12dj3200 must be calculated based on system parameters. those items are covered in this detailed design procedure section. 8.2.2.1 calculating values of ac-coupling capacitors ac-coupling capacitors are used in the input clk+/- and jesd204b output data pairs. the capacitor values must be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively long startup biasing times, or unwanted parasitic inductance. the minimum capacitor value can be calculated based on the lowest frequency signal that will be transferred through the capacitor. given a 50- single-ended clock or data path impedance, it is good practice to set the capacitor impedance to be < 1 at the lowest frequency of interest. this ensures minimal impact on signal level at that frequency. for the clk+/- path, the minimum rated clock frequency is 800 mhz. therefore the minimum capacitor value can be calculated from: (12) setting z c = 1 and rearranging gives: (13) therefore a capacitance value of at least 199 pf is needed to provide the low frequency response for the clk+/- path. if the minimum clock frequency will be higher than 800 mhz this calculation can be revisited for that frequency. similar calculations can be done for the jesd204b output data capacitors based on the minimum frequency in that interface. capacitors should also be selected for good response at high frequencies, and with dimensions that match the high frequency signal traces they are connected to. '0201' size capacitors are frequently well suited to these applications. 8.2.3 application curves the adc12dj3200can be used in a number of different operating modes to suit multiple applications. the 3 plots that follow illustrate operation with a 497.77 mhz input signal in the following configurations: ? 6.4 gsps, single input mode, 12-bit output, jmode0 ? 3.2 gsps, dual input mode, 12-bit output, jmode2 ? 3.2 gsps with 16x decimation, dual input mode, 15+15-bit complex output, jmode11 ( ) l c c k z 1/ 2 c = p | ( ) c 1/ 2 800 mhz 1 = 1 pf 99 = p w
139 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 182. fft for 497.77 mhz input signal, 6.4 gsps, jmode0 figure 183. fft for 497.77 mhz input signal, 3.2 gsps, jmode2 figure 184. fft for 497.77 mhz input signal, 3.2 gsps, decimation-by-16, f nco = 500 mhz, jmode11
140 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 initialization set up the device and jesd204 interface requires a specific startup and alignment sequence. the general order of that sequence is listed in the following steps. 1. power up or reset the device. 2. apply stable device clk signal at desired frequency. 3. program jesd_en=0 to stop the jesd204b state machine and allow setting changes. 4. program cal_en=0 to stop the calibration state machine and allow setting changes. 5. program desired jmode. 6. program desired km1 value. km1 = k-1. 7. program sync_sel as needed. choose syncse or timestamp differential inputs. 8. configure device calibration settings as desired. select foreground or background calibration modes and offset calibration as needed. 9. program cal_en=1 to enable the calibration state machine. 10. enable over-range via ovr_en and adjust settings if desired. 11. program jesd_en=1 to re-start the jesd204b state machine and allow the link to re-start. 12. jesd204b interface will operate in response to applied sync signal from receiver. 13. program cal_soft_trig=0. 14. program cal_soft_trig=1 to initiate a calibration. 9 power supply recommendations the device requires 2 different power supply voltages. 1.9 v dc is required for the va19 power bus and 1.1 v dc is required for the va11 and vd11 power buses. the power supply voltages must be low noise and provide the needed current to achieve rated device performance. there are two recommended power supply architectures: 1. stepdown using high efficiency switching converters, followed by a second stage of regulation to provide switching noise reduction and improved voltage accuracy. 2. direct stepdown the final adc supply voltage using high efficiency switching converters. this approach provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent degraded adc performance. ti webench ? power designer can be used to select and design the individual power supply elements needed: http://www.ti.com/lsds/ti/analog/webench/power.page recommended switching regulators for the first stage include the tps62085, tps82130, tps62130a and similar devices. recommended low drop-out (ldo) linear regulators include the tps7a7200, tps74401 and similar devices. for the switcher only approach, it is critical to design the ripple filter with a notch frequency that aligns with the switching ripple frequency of the dc-dc converter. note the switching frequency reported from webench ? and design the emi filter and capacitor combination to have the notch frequency centered as needed. figure 185 and figure 186 below illustrate the two approaches:
141 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 185. example ldo linear regulator approach figure 186. example switcher-only approach power sequencing the voltage regulators should be sequenced using the power good outputs and enable inputs to ensure that the vx11 regulator is enabled after the va19 supply is good. similarly, as soon as the va19 supply drops out of regulation on power-down, the vx11 regulator will be disabled. the general requirement for the adc is that va19 vx11 during power-up, operation, and power-down. buck ldo 47 f 47 f 10 f 0.1 f 0.1 f gnd gnd gnd + gnd 5v-12v 2.2v va19 buck ldo 47 f 47 f 10 f 0.1 f 0.1 f gnd gnd gnd 1.4v va11 10 f 0.1 f 0.1 f gnd vd11 1.9v 1.1v fb fb fb fb fb = ferrite bead filter fb power good buck 10 f 10 f 10 f 0.1 f 0.1 f gnd gnd + gnd 5v-12v va19 buck 10 f 0.1 f 0.1 f gnd va11 10 f 0.1 f 0.1 f gnd vd11 1.9v 1.1v fb fb fb fb ripple filter notch frequency to match fs of buck converter fb = ferrite bead filter fb 10 f 10 f 10 f gnd 10 f ripple filter ripple filter power good
142 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated ti also recommends that va11 and vd11 are derived from a common 1.1-v regulator. this ensures that all of the 1.1-v blocks are at the same voltage, and no sequencing problems exist between these supplies. ferrite bead filters should be used to isolate any noise on the va11 and vd11 buses from affecting each- other. 10 layout 10.1 layout guidelines there are many critical signals which require specific care during board design: 1. analog input signals 2. clk and sysref 3. jesd204b data outputs ( a) a. lower 8 pairs operating at up to 12.8 gbit/sec ( b) b. upper 8 pairs operating at up to 6.4 gbit/sec 4. power connections 5. ground connections items 1, 2 and 3 must be routed for excellent signal quality at high frequencies. the following general practices should be used: 1. route using loosely coupled 100- differential traces. this will minimize impact of corners and length matching serpentines on pair impedance. 2. provide adequate pair to pair spacing to minimize crosstalk. 3. provide adequate ground plane pour spacing to minimize coupling with the high speed traces. 4. use smoothly radiused corners. avoid 45 or 90 degree bends. 5. incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. cut-out below the landing pads on one or multiple ground planes to achieve a pad size/stackup height that achieves the needed 50 ohm single ended impedance. 6. avoid routing traces near irregularities in the reference ground planes. this includes ground plane clearances associated with power and signal vias and through-hole component leads. 7. provide symmetrically located ground tie vias adjacent to any high speed signal vias. 8. when high speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top and/or bottom of the vias. if layer selection is not flexible, use back-drilled or buried/blind vias to eliminate stubs. in addition, ti recommends performing signal quality simulations of the critical signal traces before committing to fabrication. insertion loss, return loss and tdr (time domain reflectometry) evaluations should be done. the power and ground connections for the device are also very important. the following rules should be followed: 1. provide low resistance connection paths to all power and ground pins. 2. use multiple power layers if necessary to access all pins. 3. avoid narrow isolated paths which increase the connection resistance. 4. use a signal/ground/power circuit board stackup to maximum coupling between the ground and power planes.
143 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 layout example the following 3 figures provide examples of the critical traces routed on the device evm (evaluation module): figure 187. top layer routing - analog inputs, clk and sysref, da0-3, db0-3
144 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated layout example (continued) figure 188. gnd1 cutouts to optimize impedance of component pads
145 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated layout example (continued) figure 189. bottom layer routing - additional clk routing, da4-7, db4-7
146 adc12dj3200 slvsd97 ? june 2017 www.ti.com product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 148. related links parts product folder sample & buy technical documents tools & software support & community adc12dj3200 click here click here click here click here click here 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. 11.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
147 adc12dj3200 www.ti.com slvsd97 ? june 2017 product folder links: adc12dj3200 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 7-jan-2019 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples adc12dj3200aav active fcbga aav 144 1 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 adc12dj32 adc12dj3200aavt active fcbga aav 144 250 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 adc12dj32 ADC12DJ3200ZEG preview fcbga zeg 144 168 green (rohs & no sb/br) sn/pb level-3-260c-168 hr -40 to 85 adc12dj32z (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 7-jan-2019 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant adc12dj3200aavt fcbga aav 144 250 180.0 24.4 10.3 10.3 2.5 16.0 24.0 q1 package materials information www.ti.com 30-apr-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) adc12dj3200aavt fcbga aav 144 250 213.0 191.0 55.0 package materials information www.ti.com 30-apr-2018 pack materials-page 2
www.ti.com package outline c 1.94 max typ 0.405 0.325 8.8 typ 8.8 typ 0.8 typ 0.8 typ 144 x 0.51 0.41 (0.68) a 10.15 9.85 b 10.15 9.85 (0.6) typ ( 8) (0.5) (0.6) typ fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. dimension is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and seating plane are defined by the spherical crowns of the solder balls. ball a1 corner seating plane ball typ 0.2 c note 4 m l k j h g f e d c b a 1 2 3 0.15 c a b 0.08 c symm symm 4 note 3 5 6 7 8 9 10 11 12 scale 1.400
www.ti.com example board layout 144 x ( ) 0.4 (0.8) typ (0.8) typ ( ) metal 0.4 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.4 0.05 min fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: (continued) 5. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number spru811 (www.ti.com/lit/spru811). symm symm land pattern example scale:8x 1 a b c d e f g h j k l m 2 3 4 5 6 7 8 9 10 11 12 non-solder mask defined (preferred) solder mask details not to scale solder mask defined
www.ti.com example stencil design (0.8) typ (0.8) typ 144 x ( ) 0.4 fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. solder paste example based on 0.15 mm thick stencil scale:8x symm symm 1 a b c d e f g h j k l m 2 3 4 5 6 7 8 9 10 11 12
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ?as is? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti?s products are provided subject to ti?s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti?s provision of these resources does not expand or otherwise alter ti?s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2019, texas instruments incorporated

▲Up To Search▲

Price & Availability of ADC12DJ3200ZEG

	To Download ADC12DJ3200ZEG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .